mc9s12ne64 Freescale Semiconductor, Inc, mc9s12ne64 Datasheet - Page 458

• Manufacturer Part Number: mc9s12ne64
• Description: Hcs12 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 17 Background Debug Module (BDMV4)
clock cycle earlier. Synchronization between the host and target is established in this manner at the start
of every bit time.
Figure 17-7
target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the
host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten
target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic
requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1
transmission.
Because the host drives the high speedup pulses in these two cases, the rising edges look like digitally
driven signals.
The receive cases are more complicated.
system. Because the host is asynchronous to the target, there is up to one clock-cycle delay from the
host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
458
START OF BIT TIME
TARGET SYSTEM
TRANSMIT 1
TRANSMIT 0
PERCEIVED
CLOCK
HOST
HOST
shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a
SYNCHRONIZATION
UNCERTAINTY
Figure 17-7. BDM Host-to-Target Serial Bit Timing
MC9S12NE64 Data Sheet, Rev. 1.1
Figure 17-8
10 CYCLES
TARGET SENSES BIT
shows the host receiving a logic 1 from the target
Freescale Semiconductor
EARLIEST
START OF
NEXT BIT