mc9s12ne64 Freescale Semiconductor, Inc, mc9s12ne64 Datasheet - Page 390

• Manufacturer Part Number: mc9s12ne64
• Description: Hcs12 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 14 Interrupt (INTV1)
14.3.2.2
Read: Only in special modes. Reads will return either the state of the interrupt inputs of the interrupt
sub-block (WRTINT = 0) or the values written into the TEST registers (WRTINT = 1). Reads will always
return 0s in normal modes.
Write: Only in special modes and with WRTINT = 1 and CCR I mask = 1.
14.3.2.3
Read: Anytime
Write: Only if I mask in CCR = 1
390
INT[E:0]
Reset
Reset
Field
7:0
W
W
R
R
PSEL7
INTE
Interrupt TEST Bits — These registers are used in special modes for testing the interrupt logic and priority
independent of the system configuration. Each bit is used to force a specific interrupt vector by writing it to a
logic 1 state. Bits are named INTE through INT0 to indicate vectors 0xFFxE through 0xFFx0. These bits can be
written only in special modes and only with the WRTINT bit set (logic 1) in the interrupt test control register
(ITCR). In addition, I interrupts must be masked using the I bit in the CCR. In this state, the interrupt input lines
to the interrupt sub-block will be disconnected and interrupt requests will be generated only by this register.
These bits can also be read in special modes to view that an interrupt requested by a system block (such as a
peripheral block) has reached the INT module.
There is a test register implemented for every eight interrupts in the overall system. All of the test registers share
the same address and are individually selected using the value stored in the ADR[3:0] bits of the interrupt test
control register (ITCR).
Note: When ADR[3:0] have the value of 0x000F, only bits 2:0 in the ITEST register will be accessible. That is,
Interrupt Test Registers
Highest Priority I Interrupt (Optional)
0
1
7
7
vectors higher than 0xFFF4 cannot be tested using the test registers and bits 7:3 will always read as a
logic 0. If ADR[3:0] point to an unimplemented test register, writes will have no effect and reads will always
return a logic 0 value.
= Unimplemented or Reserved
= Unimplemented or Reserved
PSEL6
INTC
Figure 14-4. Highest Priority I Interrupt Register (HPRIO)
0
1
6
6
Figure 14-3. Interrupt TEST Registers (ITEST)
Table 14-3. ITEST Field Descriptions
PSEL5
INTA
MC9S12NE64 Data Sheet, Rev. 1.1
0
1
5
5
PSEL4
INT8
0
1
4
4
Description
PSEL3
INT6
0
0
3
3
PSEL2
INT4
0
0
2
2
Freescale Semiconductor
PSEL1
INT2
0
1
1
1
INT0
0
0
0
0
0