cop8ccr9 National Semiconductor Corporation, cop8ccr9 Datasheet - Page 67

• Manufacturer Part Number: cop8ccr9
• Description: 8-bit Cmos Flash Microcontroller With 32k Memory, Virtual Eeprom, 10-bit A/d And Brownout
• Manufacturer: National Semiconductor Corporation

19.0 Memory Map
xxB8
xxB9
xxBA
xxBB
xxBC
xxBD
xxBE
xxBF
xxC0
xxC1
xxC2
xxC3
xxC4
xxC5
xxC6
xxC7
xxC8
xxC9
xxCA
xxCB
xxCC
xxCD
xxCE
xxCF
xxD0
xxD1
xxD2
xxD3
xxD4
xxD5
xxD6
xxD7
xxD8
xxD9
xxDA
xxDB
xxDC
xxDD to xxDF
S/ADD REG
Address
USART Transmit Buffer (TBUF)
USART Receive Buffer (RBUF)
USART Control and Status Register
(ENU)
USART Receive Control and Status
Register (ENUR)
USART Interrupt and Clock Source
Register (ENUI)
USART Baud Register (BAUD)
USART Prescale Select Register (PSR)
Reserved for USART
Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA Lower
Byte
Timer T2 Autoload Register T2RA Upper
Byte
Timer T2 Autoload Register T2RB Lower
Byte
Timer T2 Autoload Register T2RB Upper
Byte
Timer T2 Control Register
WATCHDOG Service Register
(Reg:WDSVR)
MIWU Edge Select Register
(Reg:WKEDG)
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register (Reg:WKPND)
A/D Converter Control Register (ENAD)
A/D Converter Result Register High Byte
(ADRSTH)
A/D Converter Result Register Low Byte
(ADRSTL)
Reserved
Idle Timer Control Register (ITMR)
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Reserved
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D
Reserved for Port D
(Continued)
Contents
67
Note: Reading memory locations 0070H–007FH (Segment 0) will return all
20.0 Instruction Set
20.1 INTRODUCTION
This section defines the instruction set of the COP8 Family
members. It contains information about the instruction set
features, addressing modes and types.
20.2 INSTRUCTION FEATURES
The strength of the instruction set is based on the following
features:
• Mostly single-byte opcode instructions minimize program
• One instruction cycle for the majority of single-byte in-
• Many single-byte, multiple function instructions such as
• Three memory mapped pointers: two for register indirect
xxE0
xxE1
xxE2
xxE3 to xxE5
xxE6
xxE7
xxE8
xxE9
xxEA
xxEB
xxEC
xxED
xxEE
xxEF
xxF0 to FB
xxFC
xxFD
xxFE
xxFF
0100 to 017F
0200 to 027F
0300 to 037F
0400 to 0047F On-Chip 128 RAM Bytes
0500 to 057F
0600 to 067F
0700 to 077F
S/ADD REG
size.
structions to minimize program execution time.
DRSZ.
addressing, and one for the software stack.
Address
ones. Reading unused memory locations 0080H–0093H (Segment 0)
will return undefined data. Reading memory locations from other Seg-
ments (i.e., Segment 8, Segment 9, … etc.) will return undefined data.
Reserved
Flash Memory Write Timing Register
(PGMTIM)
ISP Key Register (ISPKEY)
Reserved
Timer T1 Autoload Register T1RB Lower
Byte
Timer T1 Autoload Register T1RB Upper
Byte
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1RA Lower
Byte
Timer T1 Autoload Register T1RA Upper
Byte
CNTRL Control Register
PSW Register
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
S Register
On-Chip 128 RAM Bytes
On-Chip 128 RAM Bytes
On-Chip 128 RAM Bytes
On-Chip 128 RAM Bytes
On-Chip 128 RAM Bytes
On-Chip 128 RAM Bytes
Contents
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