cop8ccr9 National Semiconductor Corporation, cop8ccr9 Datasheet - Page 68

• Manufacturer Part Number: cop8ccr9
• Description: 8-bit Cmos Flash Microcontroller With 32k Memory, Virtual Eeprom, 10-bit A/d And Brownout
• Manufacturer: National Semiconductor Corporation

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20.0 Instruction Set
20.3 ADDRESSING MODES
The instruction set offers a variety of methods for specifying
memory addresses. Each method is called an addressing
mode. These modes are classified into two categories: op-
erand addressing modes and transfer-of-control addressing
modes. Operand addressing modes are the various meth-
ods of specifying an address for accessing (reading or writ-
ing) data. Transfer-of-control addressing modes are used in
conjunction with jump instructions to control the execution
sequence of the software program.
20.3.1 Operand Addressing Modes
The operand of an instruction specifies what memory loca-
tion is to be affected by that instruction. Several different
operand addressing modes are available, allowing memory
locations to be specified in a variety of ways. An instruction
can specify an address directly by supplying the specific
address, or indirectly by specifying a register pointer. The
contents of the register (or in some cases, two registers)
point to the desired memory location. In the immediate
mode, the data byte to be used is contained in the instruction
itself.
Each addressing mode has its own advantages and disad-
vantages with respect to flexibility, execution speed, and
program compactness. Not all modes are available with all
instructions. The Load (LD) instruction offers the largest
number of addressing modes.
The available addressing modes are:
The addressing modes are described below. Each descrip-
tion includes an example of an assembly language instruc-
tion using the described addressing mode.
Direct. The memory address is specified directly as a byte in
the instruction. In assembly language, the direct address is
written as a numerical value (or a label that has been defined
elsewhere in the program as a numerical value).
Example: Load Accumulator Memory Direct
• Sixteen memory mapped registers that allow an opti-
• Ability to set, reset, and test any individual bit in data
• Register-Indirect LOAD and EXCHANGE instructions
• Unique instructions to optimize program size and
• Direct
• Register B or X Indirect
• Register B or X Indirect with Post-Incrementing/
• Immediate
• Immediate Short
• Indirect from Program Memory
mized implementation of certain instructions.
memory address space, including the memory-mapped
I/O ports and registers.
with optional automatic post-incrementing or decrement-
ing of the register pointer. This allows for greater effi-
ciency (both in cycle time and program code) in loading,
walking across and processing fields in data memory.
throughput efficiency. Some of these instructions are:
DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.
Decrementing
LD A,05
(Continued)
68
Register B or X Indirect. The memory address is specified
by the contents of the B Register or X register (pointer
register). In assembly language, the notation [B] or [X] speci-
fies which register serves as the pointer.
Example: Exchange Memory with Accumulator, B Indirect
Register B or X Indirect with Post-Incrementing/
Decrementing. The relevant memory address is specified
by the contents of the B Register or X register (pointer
register). The pointer register is automatically incremented
or decremented after execution, allowing easy manipulation
of memory blocks with software loops. In assembly lan-
guage, the notation [B+], [B−], [X+], or [X−] specifies which
register serves as the pointer, and whether the pointer is to
be incremented or decremented.
Example: Exchange Memory with Accumulator, B Indirect
Intermediate. The data for the operation follows the instruc-
tion opcode in program memory. In assembly language, the
number sign character (#) indicates an immediate operand.
Example: Load Accumulator Immediate
Immediate Short. This is a special case of an immediate
instruction. In the “Load B immediate” instruction, the 4-bit
immediate value in the instruction is loaded into the lower
nibble of the B register. The upper nibble of the B register is
reset to 0000 binary.
Example: Load B Register Immediate Short
Memory Location
Memory Location
Memory Location
Accumulator
Accumulator
Accumulator
Accumulator
X A,[B]
with Post-Increment
X A,[B+]
LD A,#05
LD B,#7
Reg/Data
0005 Hex
Reg/Data
0005 Hex
Reg/Data
0005 Hex
Reg/Data
Reg/Data
B Pointer
B Pointer
B Pointer
Memory
Memory
Memory
Memory
Memory
Contents
Contents
Before
12 Hex
XX Hex
Before
Contents
Contents
Contents
XX Hex
A6 Hex
Before
Before
01 Hex
87 Hex
05 Hex
Before
03 Hex
62 Hex
05 Hex
Contents
Contents
07 Hex
05 Hex
Contents
Contents
Contents
After
After
A6 Hex
A6 Hex
87 Hex
01 Hex
05 Hex
62 Hex
03 Hex
06 Hex
After
After
After