sc68c2550b NXP Semiconductors, sc68c2550b Datasheet - Page 16

• Manufacturer Part Number: sc68c2550b
• Description: Sc68c2550b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. , With 16-byte Fifos And Motorola Up Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14941
Product data sheet
7.3.2 FIFO mode
trigger level. However, the FIFO continues to fill regardless of the programmed level until
the FIFO is full. RXRDY packages transitions LOW when the FIFO reaches the trigger
level, and transitions HIGH when the FIFO empties.
Table 9:
Bit
7:6
5:4
3
2
1
Symbol
FCR[7:6]
FCR[5:4]
FCR[3]
FCR[2]
FCR[1]
FIFO Control Register bits description
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Description
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO equals
the programmed trigger level. However, the FIFO will continue to be loaded
until it is full. Refer to
not used; initialized to logic 0
DMA mode select
Transmit operation in mode ‘0’: When the SC68C2550B is in the 68C450
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO or transmit holding register, the TXRDY pin
will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after the first
character is loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC68C2550B is in mode ‘0’
(FCR[0] = logic 0), or in the FIFO mode (FCR[3] = logic 0) and there is at
least one character in the receive FIFO, the RXRDY pin will be a logic 0.
Once active, the RXRDY pin will go to a logic 1 when there are no more
characters in the receiver.
Transmit operation in mode ‘1’: When the SC68C2550B is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when
the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO
locations are empty.
Receive operation in mode ‘1’: When the SC68C2550B is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached,
or a Receive Time-Out has occurred, the RXRDY pin will go to a logic 0.
Once activated, it will go to a logic 1 after there are no more characters in
the FIFO.
XMIT FIFO reset
RCVR FIFO reset
logic 0 (or cleared) = normal default condition
logic 1 = RX trigger level
logic 0 = set DMA mode ‘0’
logic 1 = set DMA mode ‘1’
logic 0 = transmit FIFO not reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
logic 0 = receive FIFO not reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
Rev. 02 — 28 April 2005
Table
10.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC68C2550B
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