km416c256d Samsung Semiconductor, Inc., km416c256d Datasheet - Page 7

• Manufacturer Part Number: km416c256d
• Description: 256k X 16bit Cmos Dynamic Ram With Fast Page Mode
• Manufacturer: Samsung Semiconductor, Inc.

KM416C256D, KM416V256D
NOTES
10.
1.
2.
3.
4.
5.
6.
7.
8.
9.
KM416C/V256D/DL Truth Table
An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is
achieved.
Input voltage levels are Vih/Vil. V
Transition times are measured between V
Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 50pF.
Operation within the
If
Assumes that
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
t
characteristics only. If
the duration of the cycle. If
read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above con-
ditions is satisfied, the condition of the data out is indeterminate.
Either
These parameters are referenced to the CAS leading edge in ealy write cycles and to the W FALLing edge in OE controlled
write cycle and read-modify-write cycles.
Operation within the
t
WCS
RAD
RAS
t
H
RCD
L
L
L
L
L
L
L
L
,
is greater than the specified
t
t
RWD
is greater than the specified
RCH
,
or
t
LCAS
CWD
t
t
H
H
H
H
RCD
RRH
L
L
L
L
L
,
t
¡ Ã
AWD
must be satisfied for a read cycle.
t
t
t
RCD
RCD
RAD
t
WCS
and
UCAS
(max) limit insures that
(max).
(max) limit insures that
t
¡ Ã
H
H
H
H
L
L
L
L
L
CWD
t
CPWD
t
WCS
¡ Ã
IH
t
t
RAD
(min), the cycles is an early write cycle and the data output will remain high impedance for
(min) and V
are non restrictive operating parameters. They are included in the data sheet as electrical
CWD
t
RCD
(max) limit, then access time is controlled by
(min),
(max) limit, then access time is controlled exclusively by
W
H
H
H
H
H
H
L
L
L
IH
(min) and V
t
RWD
IL
(max) are reference levels for measuring timing of input signals.
t
RAC
t
RAC
¡ Ã
OE
H
H
H
H
H
H
t
L
L
L
(max) can be met.
RWD
(max) can be met.
IL
(max) and are assumed to be 5ns for all inputs.
(min),
t
DQ0 - DQ7
AWD
DQ-OUT
DQ-OUT
DQ-IN
DQ-IN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
¡ Ã
-
t
AWD
t
RCD
t
RAD
(min) and
(max) is specified as a reference point only.
(max) is specified as a reference point only. If
t
AA
DQ8-DQ15
t
.
DQ-OUT
DQ-OUT
CPWD
DQ-IN
DQ-IN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
¡ Ã
t
CPWD
t
CAC
CMOS DRAM
(min) then the cycle is a
.
Word Read
Word Write
Byte Read
Byte Read
Byte Write
Byte Write
Standby
Refresh
STATE
-
oh
or V
ol
.