km4132g271a ETC-unknow, km4132g271a Datasheet - Page 15

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

KM4132G271A
DEVICE OPERATIONS (Continued)
ister Set etc. is possible only when both banks are in idle state.
AUTO PRECHARGE
precharge. The SGRAM internally generates the timing to satisfy
t
latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A
read or burst write command is issued with low on A
is left active until a new command is asserted. Once auto pre-
charge command is given, no new commands are possible to
that particular bank until the bank achieves idle state.
BOTH BANKS PRECHARGE
charge all command. Asserting low on CS, RAS, and WE with
high on A
ment, performs precharge on both banks. At the end of t
performing precharge all, both banks are in idle state.
AUTO REFRESH
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the rows.
An auto refresh command is issued by asserting low on CS,RAS
and CAS with high on CKE and WE. The auto refresh command
can only be asserted with both banks being in idle state and the
device is not in power down mode (CKE is high in the previous
cycle). The time required to complete the auto refresh operation
is specified by "t
required can be calculated by driving "t
and them rounding up to the next higher integer. The auto
refresh command must be followed by NOP's until the auto
refresh operation
state at the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SGRAM is being used for nor-
mal data transactions. The auto refresh cycle can be performed
once in 15.6
16ms.
RAS
Entry to Power Down, Auto refresh, Self refresh and Mode reg-
The precharge operation can also be performed by using auto
Both banks can be precharged at the same time by using Pre-
The storage cells of SGRAM need to be refreshed every 16ms
(min) and "t
8
after both banks have satisfied t
§Á
RP
or a burst of 1024 auto refresh cycles once in
RC
i
" for the programmed burst length and CAS
(min)". The minimum number of clock cycles
s completed. Both banks will be in the idle
RC
" with clock cycle time
RAS
(min) require-
8
, the bank
8
. If burst
RP
after
SELF REFRESH
SGRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SGRAM. In self refresh
mode, the SGRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing is inter-
nally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE.
Once the self refresh mode is entered, only CKE state being low
matters, all the other inputs including clock are ignored to remain
in the self refresh.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP's
for a minimum time of "t
state to begin normal operation. If the system uses burst auto
refresh during normal operation, it is recommended to use burst
1024 auto refresh cycles immediately after exiting self refresh.
DEFINE SPECIAL FUNCTION(DSF)
tied to low, SGRAM functions as 128K x 32 x2 Bank SDRAM.
SGRAM can be used as an unified memory by the appropriate
DSF command. All the graphic function mode can be entered
only by setting DSF high when issuing commands which other-
wise would be normal SDRAM commands.
SDRAM functions such as RAS Active, Write, and WCBR
change to SGRAM functions such as RAS Active with WPB,
Block Write and SWCBR respectively. See the sessions below
for the graphic functions that DSF controls.
SPECIAL MODE REGISTER SET(SMRS)
color register and the other is mask register. Those usage will be
explained at "WRITE PER BIT" and "BLOCK WRITE" session.
When A
CAS and WE going low, load mask register(LMR) process is
executed and the mask registers are filled with the masks for
associated DQ's through DQ pins. And when A
high in the same cycle as CS, RAS, CAS and WE going low,
load color register(LCR) process is executed and the color regis-
ter is filled with color data for associated DQ's through the DQ
pins. If both A
cycle is required to complete the write in the mask register and
the color register at LMR and LCR respectively. The next clock
of LMR or LCR, a new commands can be issued. SMRS, com-
pared with MRS, can be issued at the active state under the con-
dition that DQ's are idle. As in write operation, SMRS accepts
the data needed through DQ pins. Therefore it should be
attended not to induce bus contention. The more detailed mate-
rials can be obtained by referring corresponding timing diagram.
The DSF controls the graphic applications of SGRAM. If DSF is
There are two kinds of special mode registers in SGRAM.One is
The self refresh is another refresh mode available in the
5
and DSF goes high in the same cycle as CS, RAS,
5
and A
6
are high at SMRS, data of mask and color
RC
" before the SGRAM reaches idle
Rev.0 (August 1997)
CMOS SGRAM
6
and DSF goes