km4132g271a ETC-unknow, km4132g271a Datasheet - Page 19

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

KM4132G271A
3. CAS Interrupt (I)
*Note :
DQ(CL2)
DQ(CL3)
1) Read interrupted by Read (BL=4)
2) Write interrupted by(Block) Write (BL=2)
4) Block Write to Block Write
(a) t
CMD
CMD
CMD
ADD
ADD
ADD
CLK
CLK
CLK
DQ
DQ
CC
1. By " Interrupt ", It is possible to stop burst read/write by external command before the end of burst.
2. t
3. t
4. Pixel :Pixel mask.
5.
6. t
7. Other Bank can be active or precharge.
By "CAS Interrupt", to stop burst read/write by CAS access ; read, write and block write.
< t
t
CCD
CDL
BWC
CC
BWC
: Clock cycle time.
: Last data in to new column address delay. (=1CLK)
: CAS to CAS delay. (=1CLK)
: Block write minimum cycle time.
Pixel
DA
BW
WR
RD
A
A
A
t
t
t
Note 3
0
Note 2
CCD
CCD
CDL
t
Note 6
NOP
Note 7
DB
WR
BWC
RD
B
X
B
0
Note 5
Note 2
Pixel
QA
DB
BW
B
0
1
Note 1
Note 4
QB
QA
0
0
QB
QB
DC
WR
C
t
t
Note 3
1
0
0
CCD
CDL
(b) t
QB
Pixel
QB
BW
D
CC
2
1
Pixel
BW
Note 2
A
Note 4
¡Ã
QB
QB
t
Note 6
BWC
t
BWC
3
2
Pixel
BW
B
QB
3
Note 4
DQ(CL2)
DQ(CL3)
3) Write interrupted by Read (BL=2)
DA
DA
WR
A
t
t
Note 3
0
0
CCD
CDL
RD
B
Note 2
Rev.0 (August 1997)
QB
0
CMOS SGRAM
QB
QB
0
1
QB
1