km4132g271a ETC-unknow, km4132g271a Datasheet - Page 3

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

KM4132G271A
PIN CONFIGURATION DESCRIPTION
CLK
CS
CKE
A
A
RAS
CAS
WE
DQMi
DQi
DSF
V
V
0
9
DD
DDQ
(BA)
~ A
/V
PIN
/V
SS
8
SSQ
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Define Special Function
Power Supply/Ground
Data Output Power/Ground
NAME
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock +t
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
Row address : RA
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t
Blocks data input when DQM active.(Byte Masking)
Data inputs/outputs are multiplexed on the same pins.
Enables write per bit, block write and special mode register set.
0
~ RA
8
SHZ
, Column address : CA
after the clock and masks the output.
INPUT FUNCTION
SS
prior to new command.
0
~ CA
Rev.0 (August 1997)
7
CMOS SGRAM