km4132g271a ETC-unknow, km4132g271a Datasheet - Page 31

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

DQ
KM4132G271A
CLOCK
Page Read & Write Cycle at Same Bank @Burst Length=4
ADDR
DQM
DSF
CKE
RAS
CAS
WE
CS
CL=2
CL=3
A
A
9
8
*Note :
Row Active
0
(A-Bank)
Ra
Ra
1
1. To write data before burst read ends, DQM should be asserted three cycle prior to write
2. Row precharge will interrupt writing. Last data input,
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
command to avoid bus contention.
before end of burst. Input data after Row precharge cycle will be masked internally.
2
t
RCD
3
(A-Bank)
Read
Ca0
4
5
(A-Bank)
Read
Cb0
Qa0
6
Qa1
Qa0
7
Qb0
Qa1
*Note 2
8
*Note 1
Qb0
Qb1
9
t
RDL
HIGH
before Row precharge, will be written.
10
(A-Bank)
Write
Cc0
Dc0
Dc0
t
CDL
11
Dc1
Dc1
12
(A-Bank)
Write
Cd0
Dd0
Dd0
13
Dd1
Dd1
14
t
Precharge
RDL
(A-Bank)
*Note 3
Rev.0 (August 1997)
15
CMOS SGRAM
16
17
: Don't care
18
19