km4132g271a ETC-unknow, km4132g271a Datasheet - Page 34

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

DQ
CLOCK
KM4132G271A
Page Read Cycle at Different Bank @Burst Length=4
ADDR
DQM
CKE
RAS
CAS
WE
DSF
CS
CL=2
CL=3
A
A
9
8
*Note :
Row Active
0
*Note 1
(A-Bank)
RAa
RAa
1
1. CS can be don't care when RAS, CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
2
3
(A-Bank)
Read
CAa
Row Active
4
(B-Bank)
RBb
RBb
5
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1
6
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1
7
(B-Bank)
Read
CBb
8
9
HIGH
LOW
10
11
(A-Bank)
Read
CAc
12
13
(B-Bank)
Read
CBd
14
Rev.0 (August 1997)
15
(A-Bank)
Read
CAe
QBd0 QBd1 QAe0 QAe1
CMOS SGRAM
16
QBd0 QBd1 QAe0 QAe1
17
Precharge
(A-Bank)
: Don't care
18
*Note 2
19