tc59lm818dmgi-37 TOSHIBA Semiconductor CORPORATION, tc59lm818dmgi-37 Datasheet
tc59lm818dmgi-37
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tc59lm818dmgi-37 Summary of contents
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... Package: 60Ball BGA, 1mm × 1mm Ball pitch (P-BGA60-0917-1.00AZ) • Lead-Free Notice: FCRAM is trademark of Fujitsu limited, Japan. TC59LM818DMGI37 220 2.5 V ± 0.125V : 1 1.9 V TC59LM818DMGI-37 Lead-Free TM is capable of high quality fast data Rev 1.2 2005-11-08 1/55 ...
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... Clock Input Write/Read Data Strobe V Power (+2 Ground SS Power (+1 DDQ (for DQ buffer) Ground V SSQ (for DQ buffer) V Reference Voltage REF NC Not Connected TC59LM818DMGI-37 PIN ASSIGNMENT (TOP VIEW) ball pitch=1.0 x 1.0mm x18 Index V DQ17 SS B DQ16 DQ15 V Q ...
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... COUNTER Note: The TC59LM818DMGI configuration is 4 Bank of 32768 × 128 × cell array with the DQ pins numbered DQ0~DQ17. To each block LATCH COLUMN DECODER LATCH WRITE ADDRESS LATCH/ ADDRESS COMPARATOR TC59LM818DMGI-37 BANK #3 BANK #2 BANK #1 BANK #0 MEMORY CELL ARRAY READ DATA BUFFER ...
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... MIN 2.375 1.7 /2 × 95% V DDQ + 0.125 V REF −0.1 −0.1 0.4 + 0.2 V REF −0.1 0.55 /2 − 0.125 V DDQ /2 − 0.125 V DDQ TC59LM818DMGI-37 RATING UNIT −0. 0.3 V DDQ + 0 −40~100 °C −55~150 °C 260 ° ± -40~100°C) ...
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... V (DC). REF + 0.7 V with a pulse width ≤ 5 ns. DDQ /2 of the transmitting device. DDQ ( CLK )} /2 ICK ICK V V (min) ISO ISO = 1 MHz 25°C) DDQ PARAMETER TC59LM818DMGI- ICK ICK (max) MIN MAX Delta 1.5 3.0 0.25 1.5 3.0 0.25 2.5 3.5 0.5 ...
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... V ≤ DDQ = 0mA ; OUT (AC) (min) ≤ V ≤ DDQ interval ; REFC (AC) (min) ≤ V ≤ DDQ REFC and TC59LM818DMGI-37 MAX UNIT 220 420 420 220 , 2005-11-08 6/55 NOTES REFI Rev 1.2 ...
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... V, T CASE PARAMETER ≤ OUT DDQ = 1.420 0.280 1.420 1.7V~1.9V) = 0.280 1.420 0.280 TC59LM818DMGI-37 MIN MAX UNIT NOTES −5 µA 5 −5 µA 5 −5 µA 5 −5.6 5.6 −9.8 mA 9.8 −2.8 2.8 Rev 1.2 2005-11-08 7/55 ...
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... CK 0 0.3 × 0.45 × 1 1 1.0 L 0.45 × 1 1 1.0 L 0.4 0.4 0.7 0.7 TC59LM818DMGI-37 (Notes MAX UNIT NOTES 3 7.5 3 7 3 0 3 0.055 × 0.17 CK 1.2 × ...
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... 200 TC59LM818DMGI-37 (Notes (continued) MAX UNIT NOTES 3,6,8 0.65 3,7,8 ns 1.95 5 µs 1 cycle ...
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... V REF V (AC) IL max ∆T (AC))/∆T IL max (DC) and V IH min IL max contains more than one decimal place, the result 3.75 ns, 0.45 × 3. 1.6875 ns is rounded up to 1.7 ns ± 0.1 V from steady state. DDQ TC59LM818DMGI-37 VALUE UNIT + 0 REF − 0 REF DDQ V V REF ...
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... V (TYP) DDQ PDEX l RSC l PDA DESL RDA MRS DESL RDA MRS op-code op-code EMRS MRS EMRS TC59LM818DMGI- RSC REFC l = 200clock cycle(min) LOCK DESL WRA REF DESL WRA REF MRS Auto Refresh cycle 2005-11-08 11/55 l REFC DESL Low Normal Operation ...
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... 1st 2nd UA TC59LM818DMGI- Refer to the Command Truth Table (AC (AC (AC Rev 1.2 2005-11-08 12/55 ...
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... CAS latency = 5 QS Low (output) DQ Hi-Z (output) CAS latency = 6 QS Low (output) DQ Hi-Z (output) Note: DQ0 to DQ17 are aligned with QS. CK DESL t CKQS QSQ TC59LM818DMGI- CKQS CKQS t t QSP QSP Low t t QSQV QSQ QSQ QSQV ...
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... CAS latency = 5 QS (output) DQ Hi-Z (output) CAS latency = 6 QS (output) DQ Hi-Z (output) Note: DQ0 to DQ17 are aligned with QS always asserted in Free Running QS mode. CK DESL t CKQS QSQ TC59LM818DMGI- CKQS CKQS t t QSP QSP t t QSQV QSQ QSQV HZ QSQ ...
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... DQSS t DSPRES t DSP t DSPREH Preamble t DSPRE DQSS DQSS t DSPRES t DSPREH Preamble t DSPRE t DQSS Low TC59LM818DMGI-37 t DSPSTH t DSS t DSPST Postamble DSS t t DSPSTH DSS DSP DSP DSPST Postamble ...
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... I Timing REFI PAUSE XXXX CLK CLK Input (control & addresses) Command Note: “I ” means “I XXXX REFI PAUSE I ”, “I ”, “I ”, etc. RC RCD RAS TC59LM818DMGI- Command Rev 1.2 2005-11-08 16/55 ...
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... BA1~BA0 A14~ × × × BA1~ FN A14 A13 BA0 × × VW0 VW1 VW0 TC59LM818DMGI-37 A14~ × × × A12~ A10~A9 A8 A11 × × × × × × A6~A0 ...
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... CURRENT CS FN STATE n − × Standby × × Power Down L L × Power Down TC59LM818DMGI- A6~A0 × × × BA1~BA0 A14~ A6~A0 NOTES × × × × × × × × × × BA1~BA0 A14~A9 ...
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... H PDEX × × L TC59LM818DMGI-37 ACTION NOTES NOP Row activate for Read Row activate for Write Power Down Entry Illegal Refer to Power Down State Begin Read Illegal Invalid Begin Write Auto-Refresh Illegal ...
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... Reserved Reserved *4 *4 BA0 A14~A7 A6~ TC59LM818DMGI-37 *3 A6~A4 A3 A2~ BURST TYPE (BT) 0 Sequential 1 Interleave A1 A0 BURST LENGTH (BL Reserved Reserved × × A4~A3 A2~A1 SS ...
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... PDEX ( STANDBY (IDLE) WRA RDA ACTIVE ACTIVE (RESTORE) LAL WRITE READ (BUFFER) TC59LM818DMGI-37 POWER DOWN PDEN ( MODE REGISTER MRS LAL Command input Automatic return The second command at Active state must be issued 1 clock after RDA or WRA command input. 2005-11-08 21/55 ...
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... I RC RDA LAL DESL = 4 cycles =1 cycle = 4 cycles I I RCD RAS TC59LM818DMGI- cycles I RC RDA LAL DESL =1 cycle = 4 cycles I I RCD RAS ...
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... Hi-Z (output DESL RDA LAL = 5 cycles =1 cycle I RCD TC59LM818DMGI- cycles DESL RDA LAL = 5 cycles =1 cycle I I RAS RCD ...
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... DESL RDA LAL = 6 cycles =1 cycle I I RAS RCD TC59LM818DMGI- cycles I RC DESL RDA = 6 cycles I I RAS RCD Rev 1 ...
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... I RC WRA LAL DESL = 4 cycles =1 cycle = 4 cycles I I RCD RAS TC59LM818DMGI- cycles I RC WRA LAL DESL =1 cycle = 4 cycles I I RCD RAS ...
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... I DESL WRA LAL = 5 cycles =1 cycle I RCD TC59LM818DMGI- cycles RC DESL WRA LAL = 5 cycles =1 cycle I I RAS RCD 2005-11-08 26/55 ...
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... QS (output (input DESL WRA LAL = 6 cycles =1 cycle I RAS RCD TC59LM818DMGI- cycles I RC DESL WRA = 6 cycles I I RAS RCD Rev 1 ...
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... I RC WRA LAL DESL Read data Write data TC59LM818DMGI- cycles I RC RDA LAL DESL WRA Rev 1 ...
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... QS (output Hi DESL WRA LAL Read data TC59LM818DMGI- cycles DESL RDA LAL Write data Rev 1.2 2005-11-08 29/55 ...
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... DESL WRA LAL Read data TC59LM818DMGI- cycles I RC DESL RDA Write data Rev 1 ...
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... RDA LAL Bank Bank "a" "b" (Bank"b" cycles Qa0Qa1 Qb0Qb1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1 Qb0Qb1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 TC59LM818DMGI- cycles = 2 cycles I RBD RBD RDA LAL RDA LAL RDA LAL ...
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... Bank Bank "a" "b" (Bank"b" cycles Qa0Qa1 Qb0Qb1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1 Qb0Qb1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 TC59LM818DMGI- cycles cycles cycles RBD RBD LAL RDA LAL RDA LAL RDA ...
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... RDA LAL Bank "a" (Bank"b" cycles Qa0Qa1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 TC59LM818DMGI- cycles cycles cycles RBD RBD RBD RDA LAL RDA LAL RDA LAL ...
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... UA LA Bank Bank "a" "b" (Bank"b" cycles Da0 Da1 Db0Db1 Da0 Da1Da2Da3Db0Db1Db2Db3 Da0 Da1 Db0Db1 Da0 Da1Da2Da3Db0Db1Db2Db3 TC59LM818DMGI- cycles cycles RBD RBD WRA LAL WRA LAL WRA LAL UA LA ...
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... WRA Bank Bank "a" "b" (Bank"b" cycles Da0Da1 Db0Db1 Da0Da1Da2Da3Db0Db1Db2Db3 Da0Da1 Db0Db1 Da0Da1Da2Da3Db0Db1Db2Db3 TC59LM818DMGI- cycles cycles cycles RBD RBD LAL WRA LAL WRA LAL WRA ...
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... RBD DESL WRA LAL UA LA Bank "a" (Bank"b" cycles Da0Da1 Db0Db1 Da0Da1Da2Da3Db0Db1Db2Db3 Da0Da1 Db0Db1 Da0Da1Da2Da3Db0Db1Db2Db3 TC59LM818DMGI- cycles cycles cycles RBD RBD RBD WRA LAL WRA LAL WRA LAL UA LA ...
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... Da0 Da1 Qb0 Qb1 Da0 Da1 Qb0 Qb1 Da0 Da1 Da0 Da1 Qb0 Qb1 Da0 Da1 Qb0 Qb1 Da0 Da1 TC59LM818DMGI- DESL WRA LAL RDA LAL DESL = 2 cycles ...
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... Da0 Da1 Da2 Da3 Qb0 Qb1 Da0 Da1 Da2 Da3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da2 Da3 Qb0 Qb1 Da0 Da1 Da2 Da3 TC59LM818DMGI- LAL DESL WRA LAL = 3 cycles = 1 cycle I I ...
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... Bank "a" WRA LAL DESL LA=#1 UA VW=1 VW0 = High VW1 = High Bank "a" Last three data are masked. TC59LM818DMGI- DESL D0 #1 (#0) Last one data is masked. WRA LAL DESL LA=#2 UA VW=2 VW0 = Low VW1 = High Bank " ...
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... When PD is brought to "High", a valid executable command may be applied DESL QPDH Power Down Entry (max.) to maintain the data written into cell. REFI TC59LM818DMGI- n-2 n-1 n n+1 DESL = 2 cycle , t l RC(min) REFI(max) Hi-Z Hi-Z Power Down Exit cycles later. PDA 2005-11-08 40/55 n+2 I ...
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... When PD is brought to "High", a valid executable command may be applied DESL QPDH (max.) to maintain the data written into cell. REFI TC59LM818DMGI- n-2 n-1 n n+1 DESL = 2 cycle , t l RC(min) REFI(max) cycles later. PDA 2005-11-08 41/55 n+2 I PDA RDA ...
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... DQ (output) Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/ DESL RDA MRS Valid (opcode) BA0="0" BA1="0" BL TC59LM818DMGI- cycles I RSC RDA DESL or WRA UA BA Rev 1.2 2005-11-08 42/55 15 LAL ...
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... DQ (input) Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/ DESL RDA MRS Valid (opcode) BA0="0" BA1="0" TC59LM818DMGI- cycles I RSC RDA DESL or WRA UA BA Rev 1.2 2005-11-08 43/55 ...
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... DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence DESL RDA MRS Valid (opcode) BA0="1" BA1="0" TC59LM818DMGI- cycles I RSC RDA DESL or WRA UA BA period ...
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... DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence. Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/ DESL RDA MRS Valid (opcode) BA0="1" BA1="0" TC59LM818DMGI- cycles I RSC RDA DESL or WRA UA BA period ...
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... I I RAS RCD must be meet 19 clock cycles. REFC must be satisfied WRA REF 8 Refresh cycle TC59LM818DMGI-37 n − cycles I REFC RDA DESL or WRA Low Hi cycles I REFC RDA DESL or WRA ...
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... LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or Extended Mode Register set cycle. I/O Organization CS & FN BA0 Bank #0 0 Bank #1 1 Bank #2 0 Bank #3 1 UPPER ADDRESS 18 bits A0~A14 TC59LM818DMGI- Each operation BA1 LOWER ADDRESS A0~A6 2005-11-08 47/55 Rev 1.2 ...
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... V DD DDQ V and V are power supply pins for memory core and peripheral circuits and V are power supply pins for the output buffer. DDQ SSQ REFERENCE VOLTAGE: V REF V is reference voltage for all input signals. REF , SSQ TC59LM818DMGI-37 Rev 1.2 2005-11-08 48/55 ...
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... PD , CLK, CLK and QS. Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued for l cycle after PD goes high. The Power Down exit function is asynchronous operation. TC59LM818DMGI-37 PDA Rev 1.2 ...
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... When the A3 bit is “1”, Interleave mode is selected. Both burst types support burst length of 2 and 4 words. BA1 BA0 Mode Register Set 0 0 Regular MRS 0 1 Extended MRS × 1 Reserved A1 A0 BURST LENGTH 0 0 Reserved Reserved × × Reserved A3 BURST TYPE 0 Sequential 1 Interleave TC59LM818DMGI-37 2 words 4 words 2005-11-08 50/55 Rev 1.2 ...
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... Addressing sequence for Interleave mode ACCESS ADDRESS CAS LATENCY TC59LM818DMGI-37 Data Data Data BURST LENGTH 2 words 0 4 words 0 Reserved Reserved Reserved Reserved Reserved 2005-11-08 51/55 Data 3 Rev 1.2 ...
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... These bits are reserved for future operations and must be set to “0” for normal operation. DQ OUTPUT DRIVER IMPEDANCE CONTROL Normal Output Driver 0 1 Strong Output Driver 1 0 Weak Output Driver 1 1 Reserved A5 STROBE SELECT 0 Reserved 1 Reserved 0 Unidirectional DS/QS mode 1 Unidirectional DS/Free running QS mode TC59LM818DMGI-37 Rev 1.2 2005-11-08 52/55 ...
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... PACKAGE DIMENSIONS P-BGA60-0917-1.00AZ Weight: 0.15g (typ.) 16.5 0 12.518 -0.15 0.2 S 0.5 0.05 0.08 A 1.0 TC59LM818DMGI- 1.25 Rev 1.2 2005-11-08 53/55 ...
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... REVISION HISTORY − Rev.1.2 ( Nov.8 ’2005 ) th • 1 edition released. Difference between lead product( P/N: TC59LM818DMBI37 ) and this lead-free product st is only part number and comment for “lead-free” on page 1. TC59LM818DMGI-37 Rev 1.2 2005-11-08 54/55 ...
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... The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. TC59LM818DMGI-37 030619EBA Rev 1.2 2005-11-08 55/55 ...