ak5366 AKM Semiconductor, Inc., ak5366 Datasheet - Page 31

• Manufacturer Part Number: ak5366
• Description: 24-bit 48khz ?? Adc With Selector/pga/alc
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK5366. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 0DH prior to generating a stop condition, the address
counter will “roll over” to 00H and the previous data will be overwritten.
The AK5366 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK5366 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK5366 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition,
the AK5366 ceases transmission.
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK5366 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but instead generates a stop condition, the AK5366 ceases transmission.
MS0309-E-00
SDA
SDA
S
A
R
S
T
T
Slave
Address
S
A
R
S
T
T
R/W="0"
Slave
Address
C
A
K
R/W="1"
Sub
Address(n)
A
C
K
Data(n)
Figure 20. CURRENT ADDRESS READ
Figure 21. RANDOM ADDRESS READ
C
A
K
S
T
A
R
T
S
Slave
Address
C
A
K
R/W="1"
Data(n+1)
C
A
K
- 31 -
Data(n)
A
C
K
Data(n+2)
A
C
K
Data(n+1)
C
A
K
C
A
K
A
C
K
Data(n+x)
A
C
K
Data(n+x)
C
A
K
O
S
T
P
P
[AK5366 ]
A
C
K
S
O
P
P
2004/05
T