ak5354 AKM Semiconductor, Inc., ak5354 Datasheet - Page 9

• Manufacturer Part Number: ak5354
• Description: Low Power 20bit ?? Adc With Pga
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
The clocks that are required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (40fs∼). The master clock
(MCLK) should be synchronized with LRCK but the phase is free of care. The frequency of MCLK can be input 256fs or
384fs. When the 384fs is input, the internal master clock is divided into 2/3 automatically.
*fs is sampling frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever ADC is in operation. If these clocks
are not provided, the AK5354 may draw excess current and it is not possible to operate properly because utilizes dynamic
refreshed internally. If the external clocks are not present, the AK5354 should be in the power-down mode.
Using SDTO, BCLK and LRCK pins are connected to external system. Audio data format has two kinds of mode, the data
format is MSB-first, 2’s compliment. Setting by DIF bit. The initial value is DIF = “0”.
The AK5354 has a Digital High Pass Filter (HPF) to cancel DC-offset in ADC and IPGA. The cut-off frequency of the
HPF is 3.4Hz at fs=44.1kHz. It also scales with the sampling frequency (fs). And digital HPF can be selected by ON/OFF
of HPF bit.
MS0054-E-02
LRCK
BCLK(64fs)
SDTO(o)
LRCK
BCLK(64fs)
SDTO(o)
System Clock
Audio Data I/F Format
Digital High Pass Filter
0
0
19:MSB, 0:LSB
19
1
1
18
19 18
19:MSB, 0:LSB
No.
0
1
2
2
3
DIF bit
8
12
19
0
1
7
1
13
Lch Data
20
6
0
14
21
Lch Data
20bit MSB justified
Figure 6. Audio Data Format (No.0)
Figure 7. Audio Data Format (No.1)
I
SDTO (ADC)
2
22
S Compatible
Table 1. Audio Data Format
0
OPERATION OVERVIEW
20
23
21
24
25
- 9 -
31
Lch: “H”, Rch: “L”
Lch: “L”, Rch: “H”
0
0
19 18
1
1
19 18
LRCK
2
2
18
8
12
19
7
1
13
Rch Data
20
6
0
14
21
Rch Data
BCLK
≥ 40fs
≥ 40fs
22
0
20
23
21
24
25
31
[AK5354]
2004/12
0
0
19
1
1