ak5383 AKM Semiconductor, Inc., ak5383 Datasheet - Page 11

• Manufacturer Part Number: ak5383
• Description: Enhanced Dual Bit 96 Khz 24-bit Adc
• Manufacturer: AKM Semiconductor, Inc.

n System Clock Input
The external clocks which are required to operate the AK5383 are MCLK, LRCK(fs), SCLK. MCLK should be
synchronized with LRCK but the phase is free of care. MCLK should be 256fs in normal sampling mode(DFS="L") and
double sampling mode needs 128fs as MCLK. Table 2 illustrates standard audio word rates and corresponding frequencies
used in the AK5383.
As the AK5383 includes the phase detect circuit for LRCK, the AK5383 is reset automatically when the synchronization
is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up.
All external clocks must be present unless RST ="L", otherwise excessive current may result from abnormal operation of
internal dynamic logic.
n Serial Data Interface
The AK5383 supports four serial data formats which can be selected via SMODE1 and SMODE2 pins(Table 3). The data
format is MSB-first, 2's complement.
M0049-E-03
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Speed
LRCK (max)
SCLK
MCLK
SMODE2
32.0kHz
44.1kHz
48.0kHz
96.0kHz
Table 2. Examples of System Clock Frequency
fs
L
H
H
L
OPERATION OVERVIEW
Table 3. Serial I/F Format
Table 1. System Clocks
SMODE1 Mode
11.2896MHz
12.2880MHz
12.2880MHz
8.1920MHz
Normal(DFS ="L")
MCLK
H
H
L
L
- 11 -
~128fs
54kHz
256fs
Slave Mode
Master Mode
I
I
2
2
S Slave Mode
S Master Mode
5.6448MHz
6.1440MHz
6.1440MHz
4.0960MHz
SCLK
Double(DFS ="H")
108kHz
~64fs
128fs
Lch = H, Rch =L
Lch =H, Rch =L
Lch =L, Rch =H
Lch =L, Rch =H
LRCK
2000/4