ak5383 AKM Semiconductor, Inc., ak5383 Datasheet - Page 4

• Manufacturer Part Number: ak5383
• Description: Enhanced Dual Bit 96 Khz 24-bit Adc
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
Note: All digital inputs should not be left floating.
M0049-E-03
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SCLK
SDATA
FSYNC
MCLK
DFS
HPFE
TEST
BGND
AGND
VA
AINR-
AINR+
VCOMR
GNDR
VREFR
I/O
I/O
O
O
O
I
I
I
I
-
-
-
I
I
-
Serial Data Clock Pin
Serial Data Output Pin
Master Clock Input Pin
Double Speed Sampling Mode Pin
High Pass Filter Enable Pin
Test Pin ( pull-down pin)
Substrate Ground Pin, 0V
Analog Ground Pin, 0V
Analog Supply Pin, 5V
Rch Analog negative input Pin
Rch Common Voltage Pin, 2.75V
Rch Reference Ground Pin, 0V
Rch Reference Voltage Pin, 3.75V
Frame Synchronization Signal Pin
Rch Analog positive input Pin
MSB first, 2's complement. SDATA stays "L" during reset.
Data is clocked out on the falling edge of SCLK.
Slave mode:
Master mode:
Slave mode:
Master mode:
256fs at DFS="L", 128fs at DFS="H".
"L": Normal Speed
"H": Double Speed
"L": Disable
"H": Enable
Should be connected to GND.
Normally connected to GNDR with a 10µF electrolytic capacitor and a 0.1µF
ceramic capacitor
Don’t care.
SCLK requires more than 48fs clock.
SCLK outputs a 128fs(DFS="L") or 64fs(DFS="H") clock.
SCLK stays "L" during reset.
When "H", the data bits are clocked out on SDATA. In I
FSYNC outputs 2fs clock. FSYNC stays "L" during reset.
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S mode, FSYNC is
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