xr16v2752il Exar Corporation, xr16v2752il Datasheet
xr16v2752il
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xr16v2752il Summary of contents
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JULY 2007 GENERAL DESCRIPTION 1 The XR16V2752 (V2752 high performance dual universal asynchronous receiver and transmitter (UART) with 64 byte TX and RX FIFOs. The device operates from 2.25 to 3.6 volts with 5 Volt tolerant inputs and ...
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... XTAL1 11 GND 12 XTAL2 CHSEL 17 INTB XTAL1 XTAL2 CHSEL ORDERING INFORMATION ART UMBER XR16V2752IL XR16V2752IJ 44-Lead PLCC XR16V2752 44-pin PLCC XR16V2752 21 4 32-pin QFN CTSB ACKAGE ...
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REV. 1.0.2 PIN DESCRIPTIONS Pin Description 32-QFN 44-PLCC N AME DATA BUS INTERFACE ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Pin Description 32-QFN 44-PLCC N AME RXA 24 39 RTSA CTSA DTRA DSRA CDA RIA ...
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REV. 1.0.2 Pin Description 32-QFN 44-PLCC N AME RTSB CTSB DTRB DSRB CDB RIB MFB ANCILLARY SIGNALS XTAL1 4 11 ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 1.0 PRODUCT DESCRIPTION The XR16V2752 (V2752) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device configuration registers. The ...
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REV. 1.0.2 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The V2752 data interface supports the Intel compatible types ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO CS 2.6 Channel A and B Internal Registers Each UART channel in the V2752 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration ...
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REV. 1.0.2 2.8 INTA and INTB Outputs The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup. Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see through 22. ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency tolerance) connected externally between ...
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REV. 1.0 IGURE AUD ATE ENERATOR Crystal XTAL1 Osc/ XTAL2 Buffer ABLE YPICAL DATA RATES WITH A Required D IVISOR FOR Output Data 16x Clock O Rate (Decimal) 400 3750 2400 625 ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.11 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with ...
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REV. 1.0 IGURE RANSMITTER PERATION IN Transmit Data Byte Auto CTS Flow Control (CTS# pin) Flow Control Characters (Xoff1/2 and Xon1/2 Reg. Auto Software Flow Control 16X or 8X Clock (EMSR bit-7) 2.12 Receiver The receiver ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO IGURE ECEIVER PERATION IN NON it rro r R ece ive T ...
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REV. 1.0.2 2.13 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 10. A RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 ...
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REV. 1.0.2 2.17 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the V2752 will halt transmission (TX) as soon as ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.19 Infrared Mode The V2752 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a ...
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REV. 1.0.2 2.20 Sleep Mode with Auto Wake-Up The V2752 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be satisfied ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.21 Internal Loopback The V2752 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions ...
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REV. 1.0.2 3.0 UART INTERNAL REGISTERS Each of the UART channel in the V2752 has its own set of configuration registers selected by address lines A0, A1 and A2 with CS# or CHSEL selecting the channel. The complete register set ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO . ABLE NTERNAL EGISTERS DDRESS EG EAD A2- AME RITE RHR RD Bit THR ...
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REV. 1.0 ABLE NTERNAL EGISTERS DDRESS EG EAD A2- AME RITE DLL RD/WR Bit DLM RD/WR Bit AFR ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 4.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT and receive interrupts (IER BIT are enabled, the RHR interrupts (see ISR bits 2 and ...
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REV. 1.0.2 IER[4]: Sleep Mode Enable (requires EFR bit • Logic 0 = Disable Sleep Mode (default). • Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details. IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1) ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO ] T ABLE P ISR R RIORITY EGISTER EVEL ...
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REV. 1.0.2 FCR[2]: TX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic transmit FIFO reset (default). • Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T 10: T ABLE RANSMIT AND T FCTR FCTR FCR RIGGER ABLE Table Table ...
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REV. 1.0.2 LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT LCR[3]: TX and RX Parity Select Parity or no parity ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space", LOW state). This condition remains, until disabled by ...
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REV. 1.0.2 MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit • Logic 0 = Enable the standard modem receive and transmit input/output interface (default). • Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO LSR[6]: THR and TSR Empty Flag This bit is set to a logic 1 whenever the transmitter goes idle set to logic 0 whenever either the THR or TSR contains a ...
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REV. 1.0.2 MSR[6]: RI Input Status Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO EMSR[5:4]: Extended RTS Hysteresis EMSR EMSR[6]: LSR Interrupt Mode • Logic 0 = LSR ...
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REV. 1.0.2 AFR[0]: Concurrent Write Mode When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is intended to reduce the dual UART initialization time. It can be used by the ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO FCTR[1:0]: RTS Hysteresis User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to “0” to select the next trigger level for hardware flow control. See FCTR[2]: ...
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REV. 1.0.2 EFR[3:0]: Software Flow Control Select Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits. T ABLE EFR -3 EFR -2 BIT BIT EFR C ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when ...
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REV. 1.0.2 T 16: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLM, DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up. They do not reset when the Reset Pin ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (44-PLCC) Thermal Resistance (32-QFN) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS O ...
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REV. 1.0.2 AC ELECTRICAL CHARACTERISTICS U : TA=-40 NLESS OTHERWISE NOTED S P YMBOL ARAMETER XTAL1 UART Crystal Oscillator ECLK External Clock T External Clock Time Period ECLK T Address Setup Time AS T Address Hold Time AH T Chip ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 13 IGURE LOCK IMING VIH External Clock VIL F 14 IGURE ODEM NPUT UTPUT IOW # Active RTS# Change of state DTR# CD# CTS# DSR# INT ...
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REV. 1.0 IGURE ATA US EAD IMING A0-A2 Valid Address T AS CSA#/ CSB# IOR# T RDV D0- IGURE ATA US RITE IMING A0-A2 Valid Address T AS ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 17 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX ...
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REV. 1.0 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX D0:D7 D0: Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# (Reading data out of RX FIFO) F ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 21 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up Data in TX FIFO ...
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REV. 1.0.2 PACKAGE DIMENSIONS (44 PIN PLCC Note: The control dimension is the millimeter column SYMBOL ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL INCHES MILLIMETERS MIN ...
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... Updated Ordering Information table. Corrected maximum crystal frequency at 2. MHz. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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XR16V2752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO GENERAL DESCRIPTION ................................................................................................ 1 A ............................................................................................................................................... 1 PPLICATIONS F .................................................................................................................................................... 1 EATURES F 1. XR16V2752 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT O ............................................................................................................................... ...
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REV. 1.0.2 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 25 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 25 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ 26 ...