xr16v2752il Exar Corporation, xr16v2752il Datasheet - Page 29

• Manufacturer Part Number: xr16v2752il
• Description: High Performance Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.2
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See
•
•
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format.
•
•
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
•
•
•
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
Table 11
LCR B
X
0
0
1
1
IT
-5 LCR B
for parity selection summary below.
BIT-2
0
1
1
X
0
1
0
1
IT
-4 LCR B
T
ABLE
LENGTH
5,6,7,8
W
6,7,8
0
1
1
1
1
ORD
11: P
5
IT
-3
ARITY SELECTION
29
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
Forced parity to space, “0”
Force parity to mark, “1”
S
TOP BIT LENGTH
(B
P
1 (default)
ARITY SELECTION
IT TIME
1-1/2
Even parity
Odd parity
No parity
2
(
S
))
XR16V2752