xr16v2752il Exar Corporation, xr16v2752il Datasheet - Page 3

• Manufacturer Part Number: xr16v2752il
• Description: High Performance Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

Pin Description
REV. 1.0.2
PIN DESCRIPTIONS
DATA BUS INTERFACE
MODEM OR SERIAL I/O INTERFACE
TXRDYB#
TXRDYA#
CHSEL
IOW#
N
IOR#
INTB
INTA
CS#
TXA
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
AME
32-QFN
P
32
31
30
29
28
27
14
11
10
21
23
IN
7
6
3
2
1
8
9
-
-
#
44-PLCC
P
15
14
10
24
20
18
16
34
17
32
38
IN
9
8
7
6
5
4
3
2
1
#
T
I/O
YPE
O
O
O
O
O
I
I
I
I
I
Address data lines [2:0]. These 3 address lines select one of the internal
registers in UART channel A/B during a data bus transaction.
Data bus lines [7:0] (bidirectional).
Input/Output Read Strobe (active low). The falling edge instigates an inter-
nal read cycle and retrieves the data byte from an internal register pointed
to by the address lines [A2:A0]. The data byte is placed on the data bus to
allow the host processor to read it on the rising edge.
Input/Output Write Strobe (active low). The falling edge instigates an inter-
nal write cycle and the rising edge transfers the data byte on the data bus
to an internal register pointed by the address lines.
UART chip select (active low). This function selects channel A or B in
accordance with the logical state of the CHSEL pin. This allows data to be
transferred between the user CPU and the 2752.
Channel Select - UART channel A or B is selected by the logical state of
this pin when the CS# pin is a logic 0. A logic 0 on the CHSEL selects the
UART channel B while a logic 1 selects UART channel A. Normally,
CHSEL could just be an address line from the user CPU such as A4. Bit-0
of the Alternate Function Register (AFR) can temporarily override CHSEL
function, allowing the user to write to both channel register simultaneously
with one write cycle when CS# is low. It is especially useful during the ini-
tialization routine.
UART channel A Interrupt output (active high). A logic high indicates chan-
nel A is requesting for service. For more details, see
UART channel B Interrupt output (active high). A logic high indicates chan-
nel B is requesting for service. For more details, see
UART channel A Transmitter Ready (active low). The output provides the
TX FIFO/THR status for transmit channel A. See
UART channel B Transmitter Ready (active low). The output provides the
TX FIFO/THR status for transmit channel B.
UART channel A Transmit Data or infrared encoder data. Standard trans-
mit and receive interface is enabled when MCR[6] = 0. In this mode, the
TX signal will be HIGH during reset or idle (no data). Infrared IrDA transmit
and receive interface is enabled when MCR[6] = 1. In the Infrared mode,
the inactive state (no data) for the Infrared encoder/decoder interface is
LOW. If it is not used, leave it unconnected.
3
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
D
ESCRIPTION
See
Table 2
Table
Figures 17
Figures 17
XR16V2752
2.
.
-
-
22
22
.
.