xr16v2752il Exar Corporation, xr16v2752il Datasheet - Page 51

• Manufacturer Part Number: xr16v2752il
• Description: High Performance Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.2
ABSOLUTE MAXIMUM RATINGS ................................................................................. 40
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 40
ELECTRICAL CHARACTERISTICS............................................................................... 40
PACKAGE DIMENSIONS (44 PIN PLCC) ...................................................................... 47
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9
DC E
AC E
R
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 25
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ........................................................................................ 26
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 28
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE . 30
4.8 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 32
4.9 SCRATCH PAD REGISTER (SPR) - READ/WRITE ......................................................................................... 33
4.10 ENHANCED MODE SELECT REGISTER (EMSR) ......................................................................................... 33
4.11 FIFO LEVEL REGISTER (FLVL) - READ-ONLY ............................................................................................ 34
4.12 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD) - READ/WRITE ....................................... 34
4.13 ALTERNATE FUNCTION REGISTER (AFR) - READ/WRITE ........................................................................ 34
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY....................................................................... 35
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY................................................................................. 35
4.16 TRIGGER LEVEL REGISTER (TRG) - WRITE-ONLY .................................................................................... 35
4.17 RX/TX FIFO LEVEL COUNT REGISTER (FC) - READ-ONLY ....................................................................... 35
4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE .......................................................................... 35
4.19 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 36
TA=-40o to +85oC, Vcc is 2.25V to 3.6V ............................................................................................................... 40
Unless otherwise noted: TA=-40o to +85oC, Vcc=2.25 - 3.63V, 70 pF load where applicable................................ 41
EVISION
T
T
T
T
T
T
T
T
F
F
F
F
F
F
F
F
F
F
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
IGURE
LECTRICAL
LECTRICAL
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 25
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 25
4.19.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 38
9: I
10: T
11: P
12: S
13: A
14: T
15: S
16: UART RESET CONDITIONS FOR CHANNEL A AND B ............................................................................................ 39
13. C
14. M
16. D
15. D
17. R
18. T
19. R
20. R
21. T
22. T
H
NTERRUPT
ISTORY
RANSMIT AND
RIGGER
ARITY SELECTION
CRATCHPAD
UTO
OFTWARE
RANSMIT
RANSMIT
RANSMIT
LOCK
ATA
ATA
ECEIVE
ECEIVE
ECEIVE
ODEM
C
C
RTS H
B
B
HARACTERISTICS
HARACTERISTICS
T
US
US
..................................................................................................................................... 49
T
I
IMING
NPUT
S
R
R
R
ABLE
F
R
R
R
OURCE AND
W
R
EADY
EADY
EADY
LOW
YSTERESIS
EADY
EADY
EADY
EAD
S
RITE
R
/O
WAP
............................................................................................................................................................. 42
S
ECEIVE
UTPUT
& I
& I
& I
ELECT
C
T
T
& I
& I
& I
........................................................................................................................................................ 29
IMING
ONTROL
S
IMING
NTERRUPT
NTERRUPT
NTERRUPT
ELECTION
NTERRUPT
NTERRUPT
NTERRUPT
P
FIFO T
T
................................................................................................................................................ 34
............................................................................................................................................... 36
.............................................................................................................................................. 43
RIORITY
IMING
............................................................................................................................................ 43
F
............................................................................................................. 40
............................................................................................................. 41
UNCTIONS
T
T
T
RIGGER
F
.................................................................................................................................... 33
T
T
T
IMING
IMING
IMING
OR
L
IMING
IMING
IMING
EVEL
C
HANNELS
[N
[FIFO M
[FIFO M
T
........................................................................................................................ 37
[N
[FIFO M
[FIFO M
....................................................................................................................... 26
ABLE AND
ON
ON
-FIFO M
-FIFO M
ODE
ODE
A & B ................................................................................................. 42
ODE
ODE
L
, DMA D
, DMA E
II
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
EVEL
ODE
, DMA M
, DMA M
ODE
]
S
FOR
]
ELECTION
FOR
NABLED
ISABLED
ODE
ODE
C
C
HANNELS
mm
HANNELS
D
E
]
NABLED
]
ISABLED
FOR
FOR
).............................................. 48
.......................................................................... 28
C
A & B ......................................................... 44
C
A & B ....................................................... 44
HANNELS
]
HANNELS
]
FOR
FOR
C
C
HANNELS
HANNELS
A & B......................................... 45
A & B........................................ 45
A & B ............................ 46
A & B ........................... 46
XR16V2752