xr16l2752ij Exar Corporation, xr16l2752ij Datasheet - Page 20
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xr16l2752ij
Manufacturer Part Number
xr16l2752ij
Description
2.25v To 5.5v Duart With 64-byte Fifo
Manufacturer
Exar Corporation
Datasheet
1.XR16L2752IJ.pdf
(49 pages)
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Part Number:
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Manufacturer:
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Quantity:
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XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
Each of the UART channel in the 2752 has its own set of configuration registers selected by address lines A0,
A1 and A2 with CS# and CHSEL selecting the channel. The complete register set is shown in
Table
3.0 UART INTERNAL REGISTERS
8.
A
A2 A1 A0
DDRESSES
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0 0
0 1
1 0
0 0
0 1
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1 1
1 1
0 0
0 1
1 0
0 0
0 1
1 0
1 1
0 0
T
ABLE
RHR - Receive Holding Register
THR - Transmit Holding Register
DLL - Div Latch Low Byte
DLM - Div Latch High Byte
AFR - Alternate Function Register
DREV - Device Revision Code
DVID - Device Identification Code
IER - Interrupt Enable Register
ISR - Interrupt Status Register
FCR - FIFO Control Register
LCR - Line Control Register
MCR - Modem Control Register
LSR - Line Status Register
Reserved
MSR - Modem Status Register
Reserved
SPR - Scratch Pad Register
FLVL - RX/TX FIFO Level Counter Register
EMSR - Enhanced Mode Select Register
TRG -RX/TX FIFO Trigger Level Register
FC - RX/TX FIFO Level Counter Register
FCTR - Feature Control Register
EFR - Enhanced Function Register
Xon-1 - Xon Character 1
Xon-2 - Xon Character 2
Xoff-1 - Xoff Character 1
Xoff-2 - Xoff Character 2
7: UART CHANNEL A AND B UART INTERNAL REGISTERS
16C550 C
R
EGISTER
E
NHANCED
OMPATIBLE
20
R
EGISTERS
R
EGISTERS
R
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
EAD
/W
RITE
LCR ≠ 0xBF, FCTR[6] = 0
LCR ≠ 0xBF, FCTR[6] = 1
LCR[7] = 1, LCR ≠ 0xBF
LCR[7] = 1, LCR ≠ 0xBF
DLL, DLM = 0x00,
LCR ≠ 0xBF
LCR = 0xBF
C
LCR[7] = 0
LCR[7] = 0
LCR[7] = 0
xr
OMMENTS
Table 7
REV. 1.2.1
and