xr16l2752ij Exar Corporation, xr16l2752ij Datasheet - Page 7

• Manufacturer Part Number: xr16l2752ij
• Description: 2.25v To 5.5v Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

xr
REV. 1.2.1
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 2752 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in
The 2752 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the 2752 is
operating at 2.5V, its V
transceiver that is operating at 5V. Caution: XTAL1 is not 5 volt tolerant.
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see
function in the device.
The XR16L2752 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x0A for the
XR16L2752 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01
means revision A.
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pin (CS#) allows the user to select
the UART and then using the channel select (CHSEL) pin, the user can select channel A or B to configure,
send transmit data and/or unload receive data to/from the UART. Individual channel select functions are shown
in
F
2.0 FUNCTIONAL DESCRIPTIONS
2.1
2.2
2.3
2.4
2.5
IGURE
Table
3. XR16L2750 D
CPU Interface
5-Volt Tolerant Inputs
Device Reset
Device Identification and Revision
Channel A and B Selection
1.
U A R T _ C H S E L
U A R T _ R E S E T
P in s in p a re n th e s e s b e c o m e a v a ila b le th ro u g h th e M F # p in . M F # A /B b e c o m e s R X R D Y # A /B w h e n A F R [2 :1 ] = '1 0 '. M F # A /B b e c o m e s O P 2 # A /B
w h e n A F R [2 :1 ] = '0 0 '. M F # A /B b e c o m e s B A U D O U T # A /B w h e n A F R [1 :0 ] = '0 1 '.
Table
U A R T _ IN T A
U A R T _ IN T B
U A R T _ C S #
(R X R D Y A # )
(R X R D Y B # )
T X R D Y A #
T X R D Y B #
IO W #
IO R #
16). An active high pulse of longer than 40 ns duration will be required to activate the reset
A 0
A 1
A 2
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
OH
ATA
may not be high enough to meet the requirements of the V
B
US
I
NTERCONNECTIONS
7
IO W #
IO R #
C H S E L
T X R D Y A #
(R X R D Y A # )
T X R D Y B #
(R X R D Y B # )
R E S E T
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
IN T A
IN T B
C S #
A 0
A 1
A 2
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
C h a n n e l A
C h a n n e l B
U A R T
U A R T
(B A U D O U T A # )
(B A U D O U T B # )
(O P 2 A # )
(O P 2 B # )
D S R A #
D T R A #
R T S A #
C T S A #
D T R B #
D S R B #
R T S B #
C T S B #
C D A #
C D B #
G N D
R IA #
R IB #
V C C
T X A
R X A
T X B
R X B
Figure 3
V C C
S e ria l In te rfa c e o f
S e ria l In te rfa c e o f
R S -2 3 2 , R S -4 8 5
R S -2 3 2 , R S -4 8 5
IH
of a CPU or a serial
2 7 5 0 in t
XR16L2752