xr16l2752ij Exar Corporation, xr16l2752ij Datasheet - Page 29

• Manufacturer Part Number: xr16l2752ij
• Description: 2.25v To 5.5v Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

xr
REV. 1.2.1
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space”, LOW state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
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LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
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This register is used to select specific modes of MF# operation and to allow both UART register sets to be
written concurrently.
AFR[0]: Concurrent Write Mode
When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is
intended to reduce the dual UART initialization time. It can be used by the CPU when both channels are
initialized to the same state. The external CPU can set or clear this bit by accessing either register set. When
this bit is set, the channel select pin still selects the channel to be accessed during read operations. The user
should ensure that LCR Bit-7 of both channels are in the same state before executing a concurrent write to the
registers at address 0, 1, or 2.
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AFR[2:1]: MF# Output Select
These bits select a signal function for output on the MF# A/B pins. These signal function are described as:
OP2#, BAUDOUT#, or RXRDY#. Only one signal function can be selected at a time.
AFR[7:3]: Reserved
All are initialized to logic 0.
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
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4.7
4.8
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
Logic 0 = No concurrent write (default).
Logic 1 = Register set A and B are written concurrently with a single external CPU I/O write operation.
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
Alternate Function Register (AFR) - Read/Write
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
B
IT
0
0
1
1
-2
B
IT
0
1
0
1
-1
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MF# F
OP2# (default)
BAUDOUT#
Reserved
RXRDY#
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
UNCTION
XR16L2752