xr16l2752ij Exar Corporation, xr16l2752ij Datasheet - Page 22
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xr16l2752ij
Manufacturer Part Number
xr16l2752ij
Description
2.25v To 5.5v Duart With 64-byte Fifo
Manufacturer
Exar Corporation
Datasheet
1.XR16L2752IJ.pdf
(49 pages)
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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR16L2752IJ
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
Company:
Part Number:
xr16l2752ij-F
Manufacturer:
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Company:
Part Number:
xr16l2752ij-F
Manufacturer:
Exar Corporation
Quantity:
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Part Number:
xr16l2752ij-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
See “Receiver” on page 12.
See “Transmitter” on page 11.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
A
A2-A0
DDRESS
0 1 0
0 0 0
0 0 0
0 0 1
0 0 0
0 0 1
0 0 0
0 0 1
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
T
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
ABLE
XOFF1 RD/WR
XOFF2 RD/WR
DREV
XON1 RD/WR
XON2 RD/WR
FCTR RD/WR
N
DVID
DLM
TRG
AFR
EFR
R
DLL
FC
AME
EG
8: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR
RD/WR
RD/WR
R
W
WR
RD
RD
RD
EAD
RITE
/
Enable
RX/TX
Mode
B
Rsvd
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Auto
Bit-7
Bit-7
Bit-7
Bit-7
CTS
IT
0
-7
SCPAD
Enable
Swap
B
Rsvd
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Auto
RTS
Bit-6
Bit-6
Bit-6
Bit-6
IT
0
-6
Baud Rate Generator Divisor
Enhanced Registers
Special
Select
Table
B
Rsvd
Char
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-1
Bit-5
Bit-5
Bit-5
Bit-5
Trig
IT
0
-5
22
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
Enable
Table
B
Rsvd
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-0
Bit-4
Bit-4
Bit-4
Bit-4
Trig
IT
0
-4
S
HADED BITS ARE ENABLED WHEN
Control
RS485
Direc-
B
Rsvd
ware
Flow
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Auto
Soft-
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
tion
IT
1
-3
RXRDY#
RX IR
B
Input
Bit-2
Bit-2
Select
Bit-2
Bit-2
Bit-2
Soft-
ware
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
Inv.
IT
0
-2
Baudout#
B
Select
Soft-
ware
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Auto
RTS
Hyst
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Cntl
IT
1
-1
rent Write
Concur-
B
ware
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Auto
Bit-0
Soft-
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
RTS
Hyst
Cntl
EFR B
IT
0
-0
xr
IT
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR=0
-4=1
DLM=0x00
LCR[7] = 1
LCR[7] = 1
DLL=0x00
C
OMMENT
REV. 1.2.1
X
BF