xr16l784iv Exar Corporation, xr16l784iv Datasheet - Page 13

• Manufacturer Part Number: xr16l784iv
• Description: High Performance 2.97v To 5.5v Quad Uart
• Manufacturer: Exar Corporation

xr
REV. 1.2.2
Automatic CTS/DSR flow control is used to prevent data overrun to the remote receiver FIFO. The CTS/DSR
pin is monitored to suspend/restart local transmitter. The flow control features are individually selected to fit
specific application requirement (see
•
•
With the Auto CTS or Auto DTR function enabled, the UART will suspend transmission as soon as the stop bit
of the character in the Transmit Shift Register has been shifted out. Transmission is resumed after the CTS#/
DTR# input is re-asserted (logic 0), indicating more data may be sent.
•
F
2.10.1
IGURE
Select CTS (and RTS) or DSR (and DTR) through MCR bit-2.
Enable auto CTS/DSR flow control using EFR bit-7.
If used, enable CTS/DSR interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt
when the CTS#/DSR# pin makes a transition: ISR bit-5 will be set to a logic 1, and UART will suspend TX
transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed
after the CTS#/DSR# input returns LOW, indicating more data may be sent.
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
10. A
(RXA FIFO
CTSB#
RXA FIFO
Interrupt)
RTSA#
Auto CTS/DSR Flow Control
TXB
INTA
Trigger Reached
UTO
Receiver FIFO
Trigger Level
Local UART
Transmitter
Auto CTS
Auto RTS
UARTA
Monitor
RTS/DTR
Data Starts
Receive
Data
Assert RTS# to Begin
1
AND
2
Transmission
Trigger Level
3
4
RX FIFO
CTS/DSR F
RTSA#
TXA
CTSA#
RXA
ON
Figure
ON
10):
LOW
5
7
Threshold
C
RTS High
ONTROL
13
6
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
8
OFF
Suspend
O
OFF
PERATION
RTSB#
CTSB#
Threshold
RTS Low
RXB
TXB
Restart
9
10
11
Trigger Reached
Remote UART
ON
Trigger Level
Receiver FIFO
12
Auto CTS
Auto RTS
Transmitter
UARTB
Monitor
ON
Trigger Level
RX FIFO
RTSCTS1
XR16L784