xr16l784iv Exar Corporation, xr16l784iv Datasheet - Page 38
![no-image](/images/manufacturer_photos/0/2/243/exar_corporation_sml.jpg)
xr16l784iv
Manufacturer Part Number
xr16l784iv
Description
High Performance 2.97v To 5.5v Quad Uart
Manufacturer
Exar Corporation
Datasheet
1.XR16L784IV.pdf
(52 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
xr16l784iv-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
xr16l784iv-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
XR16L784
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Combinations of software flow control can be selected by programming these bits.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the
new values. This feature prevents legacy software from altering or overwriting the enhanced functions once
set. Normally, it is recommended to leave it enabled, logic 1.
•
•
4.13
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are set to a logic 0 to be compatible with ST16C554 mode (default).
Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features are
enabled.
EFR
C
ONT
X
X
X
0
0
1
0
1
1
0
1
0
Enhanced Feature Register (EFR) - Read/Write
BIT
-3
-3
EFR
C
ONT
X
X
X
0
0
0
1
1
0
1
1
0
BIT
-2
-2
T
ABLE
EFR
C
ONT
18: S
X
X
X
X
0
0
1
0
1
1
1
1
BIT
-1
-1
OFTWARE
Table 18
EFR
C
ONT
X
X
X
X
0
0
0
1
1
1
1
1
F
BIT
38
LOW
-0
). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
-0
C
No TX and RX flow control (default and reset)
No transmit flow control
Transmit Xon1/Xoff1
Transmit Xon2/Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1/Xoff1
Receiver compares Xon2/Xoff2
Transmit Xon1/ Xoff1,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon2/Xoff2,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
No transmit flow control,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
ONTROL
T
RANSMIT AND
F
UNCTIONS
R
ECEIVE
S
OFTWARE
xr
F
LOW
C
REV. 1.2.2
ONTROL