xr16l784iv Exar Corporation, xr16l784iv Datasheet - Page 37
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xr16l784iv
Manufacturer Part Number
xr16l784iv
Description
High Performance 2.97v To 5.5v Quad Uart
Manufacturer
Exar Corporation
Datasheet
1.XR16L784IV.pdf
(52 pages)
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Quantity
Price
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Part Number:
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Manufacturer:
Exar Corporation
Quantity:
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Part Number:
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Manufacturer:
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xr
REV. 1.2.2
FCTR[4]: Infrared RX Input Logic Select
•
•
FCTR[5]: Auto RS485 Enable
Auto RS485 half duplex control enable/disable.
•
•
FCTR[7:6]: TX and RX FIFO Trigger Table Select
These 2 bits select the transmit and receive FIFO trigger level table A, B, C or D. When table A, B, or C is
selected the auto RTS flow control trigger level is set to "next FIFO trigger level" for compatibility to ST16C550
and ST16C650 series. RTS/DTR# triggers on the next level of the RX FIFO trigger level, in another word, one
FIFO level above and one FIFO level below. See in
bit 6-7, i.e. if Table C is used on the receiver with RX FIFO trigger level set to 56 bytes, RTS/DTR# output will
de-assert at 60 and re-assert at 16.
Logic 0 = Select RX input as active high encoded IrDA data, normal, (default).
Logic 1 = Select RX input as active low encoded IrDA data, inverted.
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out.
Logic 1 = Enable Auto RS485 half duplex direction control. RTS# output changes its logic level from HIGH to
LOW when finished sending the last stop bit of the last character out of the TSR register. It changes from
LOW to HIGH when a data byte is loaded into the THR or transmit FIFO. The change to HIGH occurs prior
sending the start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register
(TSR) empty.
FCTR B
T
ABLE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IT
-3
17: 16 S
FCTR B
ELECTABLE
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
IT
-2
H
YSTERESIS
FCTR B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Table 14
L
IT
EVELS
37
-1
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
W
for complete selection with FCR bit 4-5 and FCTR
HEN
FCTR B
T
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RIGGER
IT
-0
T
ABLE
RTS/DTR H
-D
(
IS
CHARACTERS
S
+/- 16
+/- 24
+/- 32
+/- 12
+/- 20
+/- 28
+/- 36
+/- 40
+/- 44
+/- 48
+/- 52
+/- 4
+/- 6
+/- 8
+/- 8
ELECTED
0
YSTERESIS
)
XR16L784