xr16l784iv Exar Corporation, xr16l784iv Datasheet - Page 51

• Manufacturer Part Number: xr16l784iv
• Description: High Performance 2.97v To 5.5v Quad Uart
• Manufacturer: Exar Corporation

xr
REV. 1.2.2
3.2 UART CHANNEL CONFIGURATION REGISTERS ................................................................................................. 25
4.0 Internal Register Descriptions ........................................................................................................... 27
4.1 R
4.2 T
4.3 I
4.4 I
4.5 FIFO C
4.6 L
4.7 M
4.8 L
4.9 M
4.10 M
4.11 SCRATCH PAD REGISTER (SPR) - R
4.12 FEATURE CONTROL REGISTER (FCTR) - R
4.13 E
4.14 TXCNT[7:0]: T
4.15 TXTRG [7:0]: T
4.16 RXCNT[7:0]: R
4.17 RXTRG[7:0]: R
ABSOLUTE MAXIMUM RATINGS ................................................................................ 41
ELECTRICAL CHARACTERIISTICS ............................................................................. 41
NTERRUPT
NTERRUPT
Figure 14. The Global Interrupt Registers, INT0, INT1, INT2 and INT3 ........................................... 21
T
Figure 15. Timer/Counter circuit. ....................................................................................................... 22
T
T
T
T
T
T
T
T
T
T
DC ELECTRICAL CHARACTERISTICS ............................................................................................... 41
Figure 16. XR16L784 VOL Sink Current Chart .................................................................................. 42
Figure 17. XR16L784 VOH Source Current Chart ............................................................................. 42
AC E
Figure 18. 16 Mode (Intel) Data Bus Read and Write Timing .......................................................... 44
Figure 19. 68 Mode (Motorola) Data Bus Read and Write Timing ................................................... 45
Figure 20. Modem Input/Output Port Delay ...................................................................................... 46
Figure 21. Receive Interrupt Timing [Non-FIFO Mode] .................................................................... 46
Figure 22. Transmit Interrupt Timing [Non-FIFO Mode] .................................................................. 47
INE
INE
RANSMIT
ECEIVE
ODEM
ODEM
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
NHANCED
ODEM
C
S
3.1.2 General Purpose 16-bit Timer/Counter. [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (default
0xXX-XX-00-00) ............................................................................................................................. 22
3.1.3 8XMODE [7:0] (default 0x00) ............................................................................................... 23
3.1.4 REGA [7:0] reserved (default 0x00) ..................................................................................... 23
3.1.5 RESET [7:0] (default 0x00) .................................................................................................... 23
3.1.6 SLEEP [7:0] - (default 0x00) .................................................................................................. 24
3.1.7 Device Identification and Revision ......................................................................................... 24
3.1.8 REGB [7:0] - (default 0x00) ................................................................................................... 24
4.3.1 IER versus Receive FIFO Interrupt Mode Operation ............................................................. 27
4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation ................................................. 27
4.4.1 Interrupt Generation: ............................................................................................................. 29
4.4.2 Interrupt Clearing: .................................................................................................................. 29
TATUS
ONTROL
LECTRICAL
ONTROL
C
S
12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. S
9: UART C
10: TIMER CONTROL R
11: UART CHANNEL CONFIGURATION REGISTERS ........................................................... 25
13: I
14: T
15: P
16: A
17: 16 S
18: S
19: UART RESET CONDITIONS .............................................................................................. 40
H
S
TATUS
ONTROL
H
OLDING
TATUS
E
S
BY
OLDING
F
NABLE
TATUS
R
NTERRUPT
EATURE
RANSMIT AND
ARITY SELECTION
OFTWARE
EGISTER
UTO
R
EFR B
R
RANSMIT
R
EGISTER
ECEIVE
ECEIVE
RANSMIT
EGISTER
R
EGISTER
R
ELECTABLE
R
C
EGISTER
R
R
R
EGISTER
RS485 H
EGISTER
HARACTERISTICS
HANNEL
EGISTER
EGISTER
EGISTER
R
IT
(LSR) - R
EGISTER
FIFO L
FIFO T
-4. ........................................................................................................................ 26
FIFO L
(LCR) - R
S
F
FIFO T
(FCR) - W
(MSR) - R
OURCE AND
LOW
(MSR) - W
(MCR) - R
(RHR) - R
R
(IER) - R
(ISR) - R
(THR) - W
ALF
[3:0] I
EVEL
H
RIGGER
ECEIVE
EVEL
(EFR) - R
C
YSTERESIS
RIGGER
EAD
-
................................................................................................................ 32
ONTROL
EAD
DUPLEX
C
RITE
EGISTER
EAD
NTERRUPT
C
O
OUNTER
RITE
EAD
/W
EAD
EAD
EAD
OUNTER
L
NLY
......................................................................................................... 43
FIFO T
RITE
P
EVEL
EAD
L
O
O
RITE
RIORITY
EAD
EVEL
/W
/W
NLY
O
O
NLY
O
F
D
.............................................................................................................. 34
/W
NLY
NLY
O
NLY
L
RITE
RITE
UNCTIONS
IRECTION
/W
- W
- R
............................................................................................... 22
.......................................................................................................... 31
EVELS
NLY
RITE
- R
- W
RIGGER
........................................................................................................ 30
........................................................................................................ 34
EAD
RITE
S
RITE
EAD
..................................................................................................... 27
..................................................................................................... 28
..................................................................................................... 35
.................................................................................................... 27
.................................................................................................... 33
EAD
OURCE
RITE
L
.................................................................................................. 27
/W
................................................................................................. 36
EVEL
............................................................................................... 38
O
W
O
RITE
O
NLY
O
NLY
C
T
HEN
NLY
................................................................................ 38
II
NLY
ABLE AND
ONTROL
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
E
............................................................................. 29
..................................................................................... 36
..................................................................................... 39
NCODING AND
.................................................................................... 39
................................................................................... 39
T
.................................................................................. 39
RIGGER
D
ELAY FROM
L
EVEL
T
ABLE
C
S
LEARING
ELECTION
-D
T
IS
RANSMIT
S
ELECTED
.................................... 22
.................................. 31
HADED BITS ARE ENABLED
-
TO
-R
....................... 37
ECEIVE
XR16L784
........ 36