sc16c752-04 NXP Semiconductors, sc16c752-04 Datasheet - Page 13
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sc16c752-04
Manufacturer Part Number
sc16c752-04
Description
Sc16c752 Dual Uart With 64-byte Fifo
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C752-04.pdf
(47 pages)
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Philips Semiconductors
9397 750 11635
Product data
6.5.1 Interrupt mode operation
6.5.2 Polled mode operation
In interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of
the receiver and transmitter by an interrupt signal, INT. Therefore, it is not necessary
to continuously poll the line status register (LSR) to see if any interrupt needs to be
serviced.
In polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be
checked by polling the line status register (LSR). This mode is an alternative to the
FIFO interrupt mode of operation where the status of the receiver and transmitter is
automatically known by means of interrupts sent to the CPU.
polled mode operation.
Fig 7. Interrupt mode operation.
Fig 8. FIFO polled mode operation.
Figure 7
PROCESSOR
PROCESSOR
shows interrupt mode operation.
Rev. 04 — 20 June 2003
IOW / IOR
IOW / IOR
INT
THR
THR
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Dual UART with 64-byte FIFO
IIR
LSR
IER
IER
1
0
Figure 8
1
0
SC16C752
RHR
RHR
1
0
002aaa230
002aaa231
1
0
shows FIFO
13 of 47
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