sc16c752-04 NXP Semiconductors, sc16c752-04 Datasheet - Page 34
sc16c752-04
Manufacturer Part Number
sc16c752-04
Description
Sc16c752 Dual Uart With 64-byte Fifo
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C752-04.pdf
(47 pages)
- Current page: 34 of 47
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Philips Semiconductors
Table 26:
T
[1]
[2]
[3]
9397 750 11635
Product data
Symbol
t
t
t
t
t
t
t
t
p1
p3
(RESET)
su1
su2
su3
w1
w2
amb
Fig 13. General read timing.
, t
When in both DMA mode 0 and FIFO enable mode, the write cycle delay should be larger than one x
= 333 ns (for Baudrate
= 1 s (for Baudrate
= 4 s (for Baudrate
Applies to external clock; crystal oscillator max 24 MHz.
p2
IOWstrobe
= 40 C to +85 C; V
D0–D7
A0–A2
CSA,
CSB
IOR
Parameter
clock cycle period
clock speed
RESET pulse width
address set-up time
data set-up time
set-up time from IOW or IOR assertion
to XTAL1 clock LOW-to-HIGH transition
IOR strobe width
IOW strobe width
AC electrical characteristics
max
=
11.1 Timing diagrams
------------------------------------- -
2 Baudrate
max
max
t su1
max
= 460.8 kbits/s)
= 115.2 kbits/s)
CC
= 1.5 Mbits/s)
1
t d1
= 2.5 V, 3.3 V
max
ADDRESS
VALID
t d3
ACTIVE
ACTIVE
t w1
…continued
10% or 5 V
DATA
Rev. 04 — 20 June 2003
t d4
Conditions
t h4
t h1
10%, unless specified otherwise.
t d2
[3]
[2]
Min
10
-
200
0
16
20
77
30
2.5 V
Max
-
48
-
-
-
-
-
-
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Dual UART with 64-byte FIFO
Min
6
-
200
0
16
20
30
30
1
3.3 V and 5 V
clock cycle.
SC16C752
Max
-
80
-
-
-
-
-
-
002aaa235
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
34 of 47
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