sc16c850svibs NXP Semiconductors, sc16c850svibs Datasheet - Page 19

• Manufacturer Part Number: sc16c850svibs
• Description: 1.8 V Single Uart, 20 Mbit/s Max. With 128-byte Fifos, Infrared Irda , And Xscale Vlio Bus Interface
• Manufacturer: NXP Semiconductors

Table 7.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
A3 A2 A1 Register
Enhanced register set
0
1
1
1
1
First extra register set
0
1
1
1
Second extra register set
0
0
1
1
1
The value shown represents the register’s initialized hexadecimal value; X = not applicable.
Accessible only when LCR[7] is logic 0, and EFCR[2:1] are logic 0.
This bit is only accessible when EFR[4] is set.
Baud rate registers accessible only when LCR[7] is logic 1.
Second special registers are accessible only when EFCR[0] = 1, and EFCR[2:1] are logic 0.
Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to 0xBF, and EFCR[2:1] are logic 0.
First extra register set is only accessible when EFCR[2:1] = 01b.
Second extra register set is only accessible when EFCR[2:1] = 10b.
The SAMPR register must be programmed before the LCR register is programmed.
1
0
0
1
1
1
0
1
1
1
1
0
1
1
0
0
1
0
1
0
0
0
1
0
1
0
0
1
SC16C850SV internal registers
EFR
Xon1
Xon2
Xoff1
Xoff2
TXINTLVL
RXINTLVL
FLWCNTH
FLWCNTL
CLKPRES
SAMPR
RS485TIME
AFCR2
AFCR1
[6]
[7]
[9]
[8]
Default
00
00
00
00
00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
[1]
Bit 7
Auto CTS
bit 7
bit 15
bit 7
bit 15
bit 7
bit 7
bit 7
bit 7
reserved
reserved
bit 7
reserved
reserved
…continued
Bit 6
Auto RTS
bit 6
bit 14
bit 6
bit 14
bit 6
bit 6
bit 6
bit 6
reserved
reserved
bit 6
reserved
reserved
Bit 5
special
character
select
bit 5
bit 13
bit 5
bit 13
bit 5
bit 5
bit 5
bit 5
reserved
reserved
bit 5
RS485
RTS invert
reserved
Bit 4
Enable
IER[7:4],
ISR[5:4],
FCR[5:4],
MCR[7:5]
bit 4
bit 12
bit 4
bit 12
bit 4
bit 4
bit 4
bit 4
reserved
reserved
bit 4
Auto RS485
RTS
sleep RX
LOW
Bit 3
Cont-3 Tx,
Rx Control
bit 3
bit 11
bit 3
bit 11
bit 3
bit 3
bit 3
bit 3
bit 3
reserved
bit 3
RS485
RTS/DTR
reserved
Bit 2
Cont-2 Tx,
Rx Control
bit 2
bit 10
bit 2
bit 10
bit 2
bit 2
bit 2
bit 2
bit 2
reserved
bit 2
transmitter
disable
RTS/CTS
mapped to
DTR/DSR
Bit 1
Cont-1 Tx,
Rx Control
bit 1
bit 9
bit 1
bit 9
bit 1
bit 1
bit 1
bit 1
bit 1
bit 1
bit 1
receiver
disable
software
reset
Bit 0
Cont-0 Tx,
Rx Control
bit 0
bit 8
bit 0
bit 8
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
bit 0
9-bit enable
TSR
interrupt
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W