sc16is760ipw NXP Semiconductors, sc16is760ipw Datasheet - Page 10

• Manufacturer Part Number: sc16is760ipw
• Description: Single Uart With I2c-bus/spi Interface, 64 Bytes Of Transmit And Receive Fifos, Irda Sir Built-in Support
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16IS740_750_760_5
Product data sheet
Fig 9. RTS functional timing
(1) N = receiver FIFO trigger level.
(2) The two blocks in dashed lines cover the case where an additional character is sent, as described in
receive
FIFO
RTS
read
RX
7.2.1 Auto RTS
Figure 9
are stored in the TCR or FCR. RTS is active if the RX FIFO level is below the halt trigger
level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted.
The sending device (for example, another UART) may send an additional character after
the trigger level is reached (assuming the sending UART has another character to send)
because it may not recognize the deassertion of RTS until it has begun sending the
additional character. RTS is automatically reasserted once the receiver FIFO reaches the
resume trigger level programmed via TCR[7:4]. This reassertion allows the sending
device to resume transmission.
start
Fig 8. Autoflow control (auto RTS and auto CTS) example
character
shows RTS functional timing. The receiver FIFO trigger levels used in auto RTS
N
FIFO
FIFO
TX
RX
stop
UART 1
Rev. 05 — 16 November 2006
Single UART with I
SERIAL TO
TO SERIAL
PARALLEL
PARALLEL
CONTROL
CONTROL
FLOW
FLOW
start
character
N + 1
1
RTS
CTS
RX
TX
2
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
stop
SC16IS740/750/760
TX
CTS
RX
RTS
TO SERIAL
SERIAL TO
PARALLEL
N
PARALLEL
CONTROL
CONTROL
FLOW
FLOW
UART 2
N + 1
Section 7.2.1
© NXP B.V. 2006. All rights reserved.
002aab040
start
FIFO
FIFO
RX
TX
002aab656
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