pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet
pt7a6525
Available stocks
Related parts for pt7a6525
pt7a6525 Summary of contents
Page 1
... Digital sets, PBXs and private packet networks • C-channel controller of data network interface circuits • D-channel controller for ISDN basic access • Interprocessor communications PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller Protocol Support • Supports LAPB/LAPD/SDLC/HDLC protocol in Auto Mode • Handles Bit-Oriented functions in all modes • Modulo-8 or modulo-128 operation • ...
Page 2
... Associated with each serial channel are its own separate transmit and receive DMA request lines. Thus, the PT7A6525/6525L has a 4-channel DMA interface. A variety of programmable telecom-specific features allow the PT7A6525/6525L/6526 to be widely used in time-slot oriented PCM systems, systems designed for packet switching, and ISDN applications. 2 ...
Page 3
... Bus Configuration .............................................................................................................................. 26 Data Encoding .................................................................................................................................. 27 Special Functions .............................................................................................................................. 27 Operational Description ..................................................................................................................... 29 Registers ........................................................................................................................................... 36 Detailed Specifications ............................................................................................ 54 Absolute Maximum Ratings ............................................................................................................... 54 DC Electrical Chacarteristics ............................................................................................................. 55 AC Electrical Characteristics ............................................................................................................. 56 Power Supply and Capacitance Characteristics .................................................................................. 56 Quartz Crystal Specifications ............................................................................................................. 66 Mechanical Information ..................................................................................................................... 67 Appendix: Index of Registers ................................................................................... 70 Notes ................................................................................................................................. 71 PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller Contents 3 Data Sheet Ver:8 ...
Page 4
... D0~D7 RD/IC1 Micro WR/IC0 Processor Interface CS ALE/IM0 INT RES IM1 DRQTA DRQRA DACKA DMA Controller DRQTB DRQRB DACKB PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller Channel A Transmit Collision Detector FIFO Data Link Controller Receive FIFO Controller Transmit Collision Detector FIFO Data Link Controller Receive FIFO ...
Page 5
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 6
... Figure 2. Pin Configuration WR/IC0 RxDA 9 RTSA 10 44-Pin CTSA/CxDA 11 PLCC TxDA 12 TxDB 13 14 CTSB/CxDB RTSB 15 16 RxDB 17 RES PT7A6525J/6525LJ DRQTA RD/IC1 PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller DRQRA 39 WR/IC0 DRQTB 38 DRQRB 37 TxCLKA 36 RxCLKA 35 AxCLKA 34 RxCLKB 33 TxCLKB 32 CTSB/CxDB AxCLKB 31 DACKA 30 29 DACKB ...
Page 7
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 8
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 9
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 10
... Note: Unless otherwise stated, this entire description (including use of the word “device”) refers to the PT7A6526 communication controller, which supports a single HDLC channel. It should be understood that the PT7A6525/6525L contains two such “devices”. In addition to those bit-oriented functions that are usually included to support the HDLC protocol - such as bit stuffing, CRC checking, flag and address recognition - the PT7A6526 provides substantial procedural support ...
Page 11
... Figure 4. Link Configuration Micro- processor Slave #1 CxD TxD RxD Note: RxD-Receive Data, TxD-Transmit, CxD-Collision PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller Point-to-Point Configuration Micro- Processor Processor #1 TxD RxD TxD RxD ...
Page 12
... After receiving a frame it takes 5 clock cycles to generate the response frame and to initiate transmission. When operating in Auto Mode, the device provides substantial procedural support. PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller The following functions are performed: - updating transmit and receive counter , - evaluation of transmit and receive counter, - processing S commands, ...
Page 13
... RSTA: Receive Status Register RAL1,2: Receive Address Low1,2 RAH1,2: Receive Address High1,2 PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller transmit data pin (TxD). Transmission is initiated by setting CMDR: XTF (08H); end of transmission is indicated by EXIR: EXE (40H). In the receive direction, the data currently assembled via the receive data line (RxD) is available in the RAL1 register. ...
Page 14
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller and the data in the XFIFO enters into the information field of the frame. This is possible only when the device is in Auto Mode. For transparent frames as well (command XTF via CMDR register), the address and the control fields must be sent to the XFIFO ...
Page 15
... This acknowledgement can be contained frame. PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller If no positive acknowledgement is received during time t1, the device transmits an S command (p=1), which must be followed response (f=1). If the S response is not received, the S command process will be performed n1 times before it is terminated ...
Page 16
... Figure 5. The Protocol Process of Transmit/Receive Frames RSC(RNR) XMR Micro- processor RSC(RR), XPR XPR RME, XPR Micro- processor TIN XPR Micro- processor XPR PCE Note: I( I(N(S), N(R)), RR(X) = RR(N(R)), RNR(X) = RNR(N(R)) PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller RME, XPR WFA Local t1 Station Poll Cycle t1 Local t1 Station t1 Protocol Error WFA Local Station 16 Data Sheet ...
Page 17
... XAD1 =XAD2 = RAL1 = RAL2 Note: The broadcast address may be programmed in RAL2 if broadcasting is required. PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller • Reception of Frames The reception of frames functions identically to LAPB/LAPD operation. • Transmission of Frames The device does not transmit frames unless so instructed frame with the poll bit set, sent by the primary station ...
Page 18
... Note: The station variables (V(S)), V(R)) are not changed. PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller XIF Slave Station XPR, RME XIF XMR Slave Station XPR ...
Page 19
... Five interrupt indications can be read directly from the ISTA register and another six interrupt indications from the extended interrupt register (EXIR). After the PT7A6525/6525L requests an interrupt by setting its INT pin to low, the microprocessor must first read the interrupt status register of channel B(ISTA-B) in the associated interrupt service routine ...
Page 20
... DMA Interface The PT7A6525/6525L contains a 4-channel DMA interface for fast and effective data transfer. ...
Page 21
... RFIFO 32 Bytes 1 Inaccessible RFIFO 32 Bytes 2 Accessible Figure 9. RFIFO Configuration (Short Frame) RFIFO 32 Bytes 1 Inaccessible RFIFO 32 Bytes 2 Accessible PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller Free Block B+1 Block B Block B+1 b) After a) Prior to Acknowledgement acknowledgement Frame Frame < n ≤ 16 Frame Frame Frame Last Part ...
Page 22
... Clock Modes The PT7A6525/6525L includes an internal Oscillator (OSC), an independent Baud-Rate Generator (BRG) and Digital Phase- Locked Loop (DPLL) circuitry for each serial channel ...
Page 23
... Time-slot Number (6 Bits) CD RxCLK TxCLK Note: Pin TxCLK is low during the transmit time-slot. In extended transparent mode, the time- slot width must bits. PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller TSNR RCS2 RCS1 RCS0 TSNX XCS2 XCS1 XCS0 Clock Shift (3 Bits) 9 Bits Time-slot ...
Page 24
... TxCLK TxD RTS CTS PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller evaluated not only within the time-slot window, but also between the time-slot window CTS must be kept active even between the time-slot window until transmission of the frame has been completed. Deactivation of CTS stops data transmission immediately ...
Page 25
... B by externally connecting the AxCLKA and RxCLKB pins. The PT7A6526 also uses the RxCLKA-AxCLKA pins to connect an external quartz crystal. Figure 13 RxCLKA AxCLKA PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller Clock Mode 7 (OSC - Receive and Transit Clock from DPLL) Similar to Clock Mode 3, but BRG clock is provided by OSC. Summary The various clock mode features are summarized in Table 7. C ...
Page 26
... Note: If the bus is occupied by other transmitters and/or there is no transmit request in the device, logic 1 will be continuously transmitted at the TxDA/TxDB output. PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller Collisions During the transmission, the data transmitted from the device is compared with the data on the bus. In case that an erroneous ...
Page 27
... It is also possible to program the RTS outputs by software. After receiving permission to transmit (CTSA/CTSB) the device transmits a frame. PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller If permission to transmit is withdrawn during the transmission process, the frame is aborted (idle). After new permission to transmit is received and if all of the data are still available in the device, the terminated frame will be re-transmitted (self-recovery) without interrupting the microprocessor ...
Page 28
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller transmit/receive data stream if the serial channel is operating in a bus configuration. This method is profitable if clock recovery should be performed by DPLL. Since only NRZ data encoding is supported in a bus configuration, there are possibly long sequences without edges in the receive data stream in case of successive “ ...
Page 29
... RHR (receiver reset) command via the CMDR register. If data reception will be performed, the receiver must be activated by setting the RAC bit in MODE to 1. PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller If no Clear to Send function is provided via a modem, the CTS pin must be connected directly to ground in order to enable data transmission. ...
Page 30
... Figure 14. Flowchart of Frame Transmission in Interrupt Mode Command XTF/XIF PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller START Transmit N Pool Ready ...
Page 31
... Several frames can be transmitted in a high speed sequence without timefill. The closing flag will be immediately followed by an opening flag. The receiver can even receive frames separated by only one (shared) flag. The following figure shows the process of transmitting two concatenated frames (50 bytes and 13 bytes) to serial interface. Figure 16. Concatenated Frame Transmission in Interrupt Mode (PT7A6525/6525L/6526) Micro- processor ...
Page 32
... The following flowchart shows concatenated frame transmission. Figure 17. Flowchart of Concatenated Frame Transmission in Interrupt Mode PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller START XPR Interrupt or Transmit ...
Page 33
... Figure 18. Frame Transmission in DMA Mode CPU/DMA Interface PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller The device will request transmission from the DMA controller for N1+1 times byte frame to be transmitted, thus meeting the (N1 = 0,1...128, N2 < 32) requirement. The following figure shows an example of a DMA driven transmission sequence with a supposed frame length of 66 bytes, i ...
Page 34
... RME (Receive Message End) interrupt, indicating that the reception of one message is completed, i.e., either Figure 19. Reception of a Long Frame PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller a. one message of less than 32 bytes the last part of a message having more than 32 bytes is stored in the RFIFO. After an interrupt has been serviced, or the received data has ...
Page 35
... Figure 20. Frame Reception in DMA Mode CPU Interface PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller Before starting to receive the next frame, the microprocessor must issue an RMC Command to confirm completion of the present frame`s receive process. Otherwise, the device will not initiate further DMA cycles by activating the DRQR line ...
Page 36
... Note: PT7A6526 contains B channel only. PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 37
... ISTA register). Masked interrupts are not indicated when reading ISTA. Instead, they are internally stored and will be indicated after the corresponding MASK bits are reset. Note: In the event of an extended interrupt, no interrupt request will be generated with EXA, EXB bits masked, even though this bit is set in ISTA. PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 38
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 39
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 40
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 41
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 42
... Table 16. Description of Timer Register PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 43
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 44
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 45
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 46
... Note: RSTA corresponds to the last received HDLC frame duplicated in the RFIFO for every frame (last byte of frame). PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller - ...
Page 47
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 48
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 49
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 50
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller - ...
Page 51
... Note: This register is used in clock mode 5 only. PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 52
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 53
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 54
... DC Output Current .......................................................................... 60mA Power Dissipation ............................................................................... 2W Recommended Operating Conditions PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller +150 + ...
Page 55
... Note: O Typical figures are and are for design aid only; not production tested. PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 56
... C Input Capacitance Output Capacitance OUT Note: ± for PT7A6525/6526 Typical figures are and are for design aid only; not production tested. AC Electrical Characteristics Figure 21. Input/Output Waveform for AC Tests 2.4 2.0 0.8 0.4 Note : - Inputs are driven to 2.4V for a logical “ ...
Page 57
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 58
... Note: If DACKA/B is provide by the DMA controller, the CS and DS is not needed to cause the falling of the DRQR signal. Refer to Page 7, Table 2, the description of DACKA and DACKB. Figure 23. Diagram of Microprocessor Interface Timing in Intel Bus Mode (in Write Cycle DRQT PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 59
... Figure 24. Multiplexed Address Timing ALE Figure 25. Address Timing DACK PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 60
... Figure 26. Diagram of Microprocessor Interface Timing in Motorola Bus Mode (in Read Cycle) R DRQR Figure 27. Diagram of Microprocessor Interface Timing in Motorola Bus Mode (in Write Cycle) R DRQT PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 61
... PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 62
... Figure 29. Serial Interface Timing R Clock RxDA Clock TxDA/B TxDA/B CxDA/B CTSA/B RTSA RTSA/B RTSA/B PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 63
... Figure 30. Diagram of Strobe Timing (Clock Mode 1) RxCLK AxCLK t XSD TxCLK High Impedance TxD High Impedance TxD PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 64
... Figure 31. Diagram of Synchronization Timing (Clock Mode 5) RxCLK AxCLK TxCLK t TCD TxCLK PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 65
... Figure 32. Diagram of CD Timing RxCLK RxD AxCLK(CD) >60ns PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller ...
Page 66
... Quartz Crystal Specifications Characteristics of Quartz Crystals for the PT7A6525/6525L/6526 • Mode of oscillation • ...
Page 67
... Mechanical Information Figure 33. 44-Pin PLCC PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller 67 Data Sheet Ver:8 ...
Page 68
... Figure 34. 44-Pin MQFP PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller 68 Data Sheet ...
Page 69
... Appendix: Index of Registers Table 48. Index of Registers of PT7A6525/6525L/6526 N ...
Page 70
... Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0017(12/05) PT7A6525/6525L/6526 HDLC Controller Notes Pericom Technology Inc. Web-Site: www.pti.com.cn, www.pti-ic.com ...