pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 33

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

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• DMA Mode
Prior to data transmission, the length of the frame to be
transmitted must be programmed via the Transmit Byte Count
Registers (XBCH, XBCL). The resulting byte count equals the
programmed value plus one byte; as 12 bits are provided via
XBCH, XBCL (XBC11...XBC0). Any frame length from 1 to 4096
bytes (4 Kbytes) can be selected.
After this task, data transmission can be initiated by command
(XIF or XTF). The device will then autonomously request the
correct amount of write bus cycles by activating the DRQT line.
PT0017(12/05)
Figure 18. Frame Transmission in DMA Mode
CPU/DMA
Interface
DMA
Write
Cycles
(66)
WR(N-1)
XTF
WR
(32bytes)
WR
(32bytes)
WR
(32bytes)
XPR
DRQT(32)
DRQT(32)
DRQT(2)
33
PT7A6525/6525L/6526 HDLC Controller
The device will request transmission from the DMA controller
for N1+1 times if an N byte frame to be transmitted, thus meeting
the N = N1 x 32 + N2 (N1 = 0,1...128, N2 < 32) requirement.
The following figure shows an example of a DMA driven
transmission sequence with a supposed frame length of 66
bytes, i.e., programmed transmit byte count (XCNT) equals 65
bytes.
PT7A6525/6525L/
(65)
PT7A6526
32 bytes
32 bytes
2 bytes
Serial
Interface
Data Sheet
Ver:8