pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 25

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
Clock Mode 6 (OSC - Receive Clock from DPLL)
This clock mode is identical to Clock Mode 2, except that the
clock for the BRG is delivered by the OSC and must not be
provided externally.
Figure 13
Note:
1. The maximum permitted serial data rate in an externally clocked operating mode is 8.192 Mb/s. In an internally clocked operating
mode with an external reference clock or using internal OSC, the maximum clock rate is 12 MHz (or 19.2 MHz if the scaling factor
of the BRG is programmed to 1), and the maximum data rate will be 1200 kbit/s.
2. The ratio between the receive frequency (fr) and the transmit frequency (fx) for a channel must satisfy the condition fr/fx < 3 in
Clock Modes 0, 2 and 6; there are no restrictions on phase shift. Slower transmit data rates can be realized with receive and
transmit strobes (Clock Mode 1).
3. Clock Modes 4, 6, 7 use the internal OSC and need an external quartz crystal to be connected at the RxCLKA-AxCLKA pins. It
is unnecessary to use two separate crystals for two serial channels. Instead it is sufficient to apply a crystal to channel A and
provide the reference clock for channel B by externally connecting the AxCLKA and RxCLKB pins. The PT7A6526 also uses the
RxCLKA-AxCLKA pins to connect an external quartz crystal.
PT0017(12/05)
Table 7. Clock Modes
C
C
C
C
C
C
M
C
C
C
C
C
C
M
a h
a h
a h
a h
a h
C
C
2
o l
o l
o l
o l
o l
M
o
0
4
4
2
2
3
5
6
6
6
7
7
1
n n
n n
n n
n n
n n
C ,
R
e d
k c
k c
k c
k c
k c
0
1
M
l e
l e
l e
l e
l e
1
C
C
C
C
C
n o
n o
n o
n o
n o
T S
T S
T S
T S
T
i f
i f
i f
i f
i f
S
S
S
S
S
0
0
0
0
0
0
0
0
0
0
1
1
1
u g
u g
u g
u g
u g
C
C
C
C
C
S
AxCLKA
RxCLKA
C
C
C
C
C
a r
a r
a r
a r
a r
R
R
R
R
R
i t
i t
i t
i t
i t
I T O
I T O
I T O
I T O
I T
2
2
2
2
2
1
n o
n o
n o
n o
n o
0
0
0
0
0
0
0
0
1
1
1
1
0 /
O
R
R
R
B G
B G
B G
B G
B
x
x
x
O
O
O
O
O
R
R
R
R
R
C
C
C
S
S
S
S
S
-
-
-
-
-
L
L
L
G
C
C
C
C
C
K
K
K
D
D
D
D
D
B
B
B
B
B
B
B
B
B
C
C
C
C
C
P
P
P
P
P
R
R
R
R
R
R
R
R
R
-
-
-
-
o l
o l
o l
L
L
L
L
L
o l
o l
G
G
G
G
G
G
G
G
G
L
L
L
L
L
k c
k c
k c
k c
k c
o S
o S
o S
o S
o S
R
R
R
D
D
D
D
D
D
D
D
R C
R C
R C
R C
R
x
x
O
O
x
r u
r u
r u
r u
r u
P
P
P
P
P
P
P
P
C
C
C
E
E
E
E
E
S
S
L
L
L
L
L
L
L
L
e c
e c
e c
e c
e c
L
L
L
C
C
C
L
L
L
L
L
L
L
L
K
K
K
B
B
B
T
R
T
R
T
D
D
D
T M
T M
T M
T M
T
x
x
R
O
O
x
R
R
x
x
R
R
R
R
R
P
P
P
C
C
C
C
C
/ G
/ G
/ G
S
S
L
L
L
M
L
L
L
L
L
C
C
L
L
L
6 1
6 1
6 1
K
K
K
K
K
25
PT7A6525/6525L/6526 HDLC Controller
A
A
A
A
T
T
T
T
Clock Mode 7 (OSC - Receive and Transit Clock from DPLL)
Similar to Clock Mode 3, but BRG clock is provided by OSC.
Summary
The various clock mode features are summarized in Table 7.
Normally, 33pF capacitors are used for frequencies below
10MHz and 22pF capacitors for frequencies above
10MHz. Refer to Figure 13.
x
x
x
x
x
x
x
x
CD
CD
CD
CD
C
C
C
C
C
C
C
C
C
. . .
-
-
-
-
D
L
L
L
L
L
L
L
L
K
K
K
K
K
K
K
K
- R
- R
- R
- R
- R
A
R (
t S
t S
t S
x
t S
t S
T
C
-
-
-
-
-
-
-
-
-
-
-
o r
o r
o r
o r
o r
S
L
) A
K
e b
e b
e b
e b
e b
C
C
C
C
C
n o
n o
n o
- X
- X
- X
- X
- X
n o
n o
T
T (
x
r t
r t
r t
t S
t S
t S
t S
t S
r t
r t
T
C
-
-
-
-
-
-
-
-
-
-
-
l o
l o
l o
l o
l o
o r
o r
o r
o r
o r
S
L
) A
K
e b
e b
e b
e b
e b
o S
o S
o S
o S
o S
r u
r u
r u
r u
r u
e c
e c
e c
e c
e c
A
- F
- F
- F
- F
- F
x
y S
y S
y S
y S
y S
C
-
-
-
-
-
-
-
-
-
-
-
-
L
c n
c n
c n
c n
c n
K
T
T
B
S
B
O
O
O
O
O
D
D
Data Sheet
C -
x
R
R
O
u
u
u
u
u
V
P
P
C
/ G
/ G
p t
p t
p t
p t
p t
S
-
-
-
-
-
-
-
a i
n o
L
L
L
C
t u
t u
t u
t u
t u
6 1
L
6 1
L
K
r t
l o
B
B
B
T
R
T
R
T
T
T
T
T
T
S
D
D
D
T P
T P
T P
T P
T
x
x
R
O
O
x
R
R
x
x
m i
m i
m i
m i
m i
u o
P
P
P
C
C
C
C
C
C
C
C
C
C
/ G
/ G
/ G
S
S
L
L
L
Ver:8
L
L
L
L
L
C
C
e r
P
r e
r e
r e
r e
r e
L
L
L
6 1
6 1
6 1
K
K
K
K
K