pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 22

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Clock Modes
The PT7A6525/6525L includes an internal Oscillator (OSC), an
independent Baud-Rate Generator (BRG) and Digital Phase-
Locked Loop (DPLL) circuitry for each serial channel.
The transmit and receive clock can be generated either
• externally, and supplied via the RxCLK and/or TxCLK
• internally, by means of the
In total, there are eight different clocking modes programmable
via the CCR1 register, providing a considerable variety of clock
generation and clock pin functions, as shown in table 6.
PT0017(12/05)
The transmit clock pins (TxCLK) may also be used as an output
for clock or control signals in certain clock modes if programmed
as such via the CCR2 register (TIO bit set).
The clocking source for the DPLLs is always the internal BRG;
the scaling factor (divider) of the BRG can be programmed
through CCR2 and BGR registers within 1,2,4,6...2048.
The device system clock is always derived from the transmit
clock thus eliminating the need for additional clock sources.
Clock Mode 0 (External Clocks)
Separate, externally generated receive and transmit clock are
forwarded to the device via their respective pins.
Table 6. Overview of Clock Modes
pins, or
- OSC and/or BRG, and
- DPLL, recovering the Receive (and optionally Transmit)
T
clock from the received data stream if an external crystal
is connected to the RxCLKA-AxCLKA pins.
R
a r
C
C
T e p
T e p
T e p
T e p
T
c e
o l
o l
y
y
y
y
y
s n
i e
e p
k c
k c
m
e v
t i
R
R
T
x
x
x
B
o S
o S
o S
o S
o S
C
C
C
D
D
O
R
O
L
L
L
P
P
r u
r u
r u
r u
r u
/ G
S
S
K
K
K
L
L
C
C
e c
e c
e c
e c
e c
L
L
6 1
i P
i P
i P
s n
s n
s n
C
C
C
C
C
o l
o l
o l
o l
o l
k c
k c
k c
k c
k c
G
G
G
G
G
E
E
n I
n I
e
e
e
e
e
x
x
e n
e n
e n
e n
e n
r e t
r e t
r e t
r e t
a r
a r
a r
a r
a r
a n
a n
a n
a n
i t
i t
i t
i t
i t
y l l
y l l
y l l
y l l
n o
n o
n o
n o
n o
2
3 ,
0
M e d
M e d
M
0
M e d
M
2 ,
1 ,
3
2
1
o
o
o
o
o
6 ,
7 ,
6 ,
4
5 ,
4
e d
e d
5 ,
6 ,
7 ,
22
PT7A6525/6525L/6526 HDLC Controller
Clock Mode 1 (Receive/Transmit Strobes)
Externally generated (but identical) receive and transmit clocks
are forwarded via RxCLK pins. In addition, receive and transmit
strobes can be connected via AxCLK and TxCLK pins
respectively. The operating mode can be applied in Time Division
Multiplex applications or for adjusting disparate transmit and
receive data rates.
Clock Mode 2 (Receive CLock from DPLL)
The BRG is driven with an external clock (RxCLK ), and it delivers
a reference clock for the DPLL which then generates the receive
clock. Depending on programming of the CCR2 register (TSS
bit), the transmit clock will be either an external clock signal
(TxCLK) or the clock delivered by the BRG divided by 16. The
transmit clock can be output via TxCLK pin(CCR2: TIO = 1).
Clock Mode 3 (Receive and Transmit Clock from DPLL)
The BRG is fed with an externally generated clock via RxCLK
and supplies the reference clock for DPLL which will generate
both the receive and transmit clock. This clock can be output
via TxCLK pin.
Clock Mode 4 (OSC-Direct)
The receive and transmit clock is directly supplied by the OSC.
This clock can be output via TxCLK.
Clock Mode 5 (Time-Slots)
This operating mode is designed for application in time-slot
oriented PCM systems.
The receive and transmit clocks are identical for each channel
and must be supplied externally via RxCLK pins. The device
receives and transmits only during certain time-slots of
programmable width (1...256 bit, via RCCR and XCCR registers).
The time slot locations are determined by a frame
synchronization signal, which must be delivered to the device
via the AxCLK pin. One of up to 64 time-slots can be programmed
independently for receive and transmit direction via the RTSA,
TTSA and CCR2 registers. Together with bits XCS0 and RCS0
(LSB of clock shift) in the CCR2 register, there are nine bits that
determine the location of a time-slot.
According to the value programmed via these nine bits, the
receive/transmit window (time-slot) starts with a delay of
between 1 and 512 clock periods following the frame
synchronization signal and is active during the number of clock
periods programmed via RCCR, XCCR (number of bits to be
received/transmitted within a time-slot) as shown below.
Data Sheet
Ver:8