pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 27

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
Data Encoding
In point-to-point configurations, the device supports both NRZ
and NRZI data encoding (selectable via CCR1 register).
Accurate recovery of the clock (and consequent identification
of the bit boundaries) from received NRZ data is dependent
upon an adequate number of transitions per unit time between
one bit value to the other. However, the actual payload data -
which must be arbitrary - can, in general, have any number of
log 1s and/or log 0s in a row. In order to prevent confusion
between the data being encapsulated and its HEX 7E (01111110)
flag, the HDLC system prevents more than five log 1s in a row
from being transmitted by inserting extra log 0s into the bit
stream as necessary. A useful byproduct of this bit-stuffing
procedure is the prevention of too many log 1s in a row from
being transmitted, but it does nothing to prevent a long string
of log 0s from being transmitted. Therefore, prior to feeding
data to the HDLC system, specially designed means (such as
whitening, or pseudo-randomizing) are used to insure that
there will not be too many log 0s in a row. At the receive end, the
recovered clock allows accurate data recovery. The HDLC sys-
tem removes the extra log 0s inserted at the transmit end (along
with the other HDLC overhead information) and sends a bit
stream to its host which is identical to what was received from
the host at the transmit end. The host then reverses the data
whitening process.
Unfortunately, none of the above processing prevents six log
1s in a row from being transmitted whenever the HDLC HEX 7E
flag is needed. In order to shorten the maximum number of
successive same value bits being transmitted from six to five, a
further encoding, called differential or NRZI encoding is per-
formed just prior to transmission. Thus, this type of encoding
is especially suitable for Clock Modes 2, 3, 6, and 7, in which the
clock is recovered from the received data by means of the DPLL
circuits.
Special Functions
Modem Control Functions (RTS/CTS, CD)
The device provides two pins (RTS, CTS) per serial channel
supporting the standard of RTS-CTS modem handshaking
procedure to control the HDLC transmitters.
Data output is performed with the rising clock edge and data
input with the falling edge. A transmit request will be indicated
by outputting log 0 at the request-to-send output (RTSA/RTSB).
It is also possible to program the RTS outputs by software.
After receiving permission to transmit (CTSA/CTSB) the device
transmits a frame.
PT0017(12/05)
27
PT7A6525/6525L/6526 HDLC Controller
If permission to transmit is withdrawn during the transmission
process, the frame is aborted (idle). After new permission to
transmit is received and if all of the data are still available in the
device, the terminated frame will be re-transmitted (self-recovery)
without interrupting the microprocessor. However, if permission
to transmit is withdrawn after the 32nd byte in the information
field, the transmitter and the XFIFO are reset, the RTS output is
deactivated, and an interrupt is generated for the
microprocessor.
Carrier Detect (CD) Receiver Control
Similar to the RTS/CTS control for the transmitter, the device
supports the carrier detect modem control function for the serial
receivers if the Carrier Detect Auto Start (CAS) function is
programmed by setting the CAS bit in the XBCH register. CAS
function is always available in clock modes 0,2 and 3 via the
AxCLK pin, and in clock modes 4,6 and 7 via the TxCLK pin, but
only if this pin has been programmed as input by clearing the
TIO bit in the CCR2 register. In clock mode 1, the CD function is
not supported (see Table 7 for an overview).
If the CAS function is selected, the corresponding HDLC receiver
is enabled and data reception is started when a high level is
sampled at the CD input.
Receive Length Check Feature
The device offers the possibility to supervise the maximum
length of received frames and to terminate data reception in
case this length is exceeded.
This feature is controlled via the special Receive Length Check
Register (RLCR).
The function is enabled by setting the RC (Receive Check) bit
in RLCR and programming the maximum frame length via bits
RL6...RL0.
According to the value written to RL6...RL0, the maximum receive
length can be adjusted in multiples of 32-byte blocks as follows:
MAX. LENGTH = (RL+1) x 32
Data Sheet
Ver:8