wm8987 Wolfson Microelectronics plc, wm8987 Datasheet - Page 36

• Manufacturer Part Number: wm8987
• Description: Stereo Codec For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

WM8987L
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DIGITAL AUDIO INTERFACE
The digital audio interface is used for inputting DAC data into the WM8987L and outputting ADC data
from it. It uses five pins:
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The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8987L operates as a
master, or inputs when it is a slave (see Master and Slave Mode Operation, below).
Three different audio data formats are supported:
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All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8987L can be configured as either a master or slave mode device. As a master device the
WM8987L generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data
transfer on ADCDAT and DACDAT. In slave mode, the WM8987L responds with data to clocks it
receives over the digital audio interface. The mode can be selected by writing to the MS bit (see
Table 23). Master and slave modes are illustrated below.
Figure 11 Master Mode
Note: For optimum ADC audio performance in slave mode, the BCLK input signal should be
configured to transition at the same time as the falling edge of MCLK.
The ADCDAT digital data output is buffered inside the CODEC using a digital logic buffering block.
However, the ADCDAT buffering block is not reset by the power-on reset circuit and hence the
ADCDAT pin stage (logic high or logic low) is undefined at power up until data is clocked out from the
ADC. Implementation of either of these workarounds will ensure correct operation:
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ADCDAT: ADC data output
ADCLRC: ADC data alignment clock
DACDAT: DAC data input
DACLRC: DAC data alignment clock
BCLK: Bit clock, for synchronisation
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DSP mode
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Ensure that any external connection to the ADCDAT pin is made with the understanding
that ADCDAT pin may be driven high or low by the CODEC until ADC data is clocked out.
Tri-state the ADCDAT output pin by setting the TRI bit in R24 (Additional Control 2
register). Setting this bit will also configure ADCLRC, DACLRC and BCLK as inputs and
(as the CODEC has no internal pull-up/down resistors) the input voltage level must be set
on these pins by an external source (either the device connected to the digital audio
interface or pull-up/down resistors) to prevent excess current consumption.
Figure 12 Slave Mode
PD Rev 4.0 August 2008
Production Data
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