wm8987 Wolfson Microelectronics plc, wm8987 Datasheet - Page 41

• Manufacturer Part Number: wm8987
• Description: Stereo Codec For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

Production Data
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CLOCKING AND SAMPLE RATES
Note: The shaded bit clock cycles are present only when 24-bit mode is selected. Please refer to the
"Bit Clock Mode" description for details.
If BCLK frequency is high enough for the increased tDDA propagation delay (i.e. ADCDAT
propagation delay from BCLK falling edge) to cause an ADCDAT set-up time issue (i.e. the ADCDAT
signal is delayed such that the first bit of ADCDAT data appears during the second BCLK cycle), the
BCM[1:0] BCLK divider bits should be configured to reduce the BCLK frequency.
CLOCK OUTPUT
By default, the ADCLRC pin is the ADC word clock input/output. Under the control of ADCLRM[1:0],
register 27(1Bh) bits [8:7] the ADCLRC pin may be configured as a clock output. If ADCLRM is 01,
10 or 11 then ADCLRC pin is always an output even in slave mode or when TRI = ‘1’, (see Table 36).
The ADC then uses the DACLRC pin as its LRCLK in both master and slave modes.
Table 36 ADCLRC Clock Output
The WM8987L supports a wide range of master clock frequencies on the MCLK pin, and can
generate many commonly used audio sample rates directly from the master clock. The ADC and
DAC do not need to run at the same sample rate; several different combinations are possible.
There are two clocking modes:
•
•
Table 37 Clocking and Sample Rate Control
The clocking of the WM8987L is controlled using the CLKDIV2, USB, and SR control bits. Setting the
CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode.
Each value of SR[4:0] selects one combination of MCLK division ratios and hence one combination
of sample rates (see next page). Since all sample rates are generated by dividing MCLK, their
accuracy depends on the accuracy of MCLK. If MCLK changes, the sample rates change
proportionately.
Note that some sample rates (e.g. 44.1kHz in USB mode) are approximated, i.e. they differ from their
target value by a very small amount. This is not audible, as the maximum deviation is only 0.27%
(8.0214kHz instead of 8kHz in USB mode). By comparison, a half-tone step corresponds to a 5.9%
change in pitch.
The SR[4:0] bits must be set to configure the appropriate ADC and DAC sample rates in both master
and slave mode.
Note: When the ADC is configured at a sample rate of 88.2, 88.235 or 96kHZ (SR[4:0]), the ADC
right channel data output will be delayed by one sample relative to the left channel data.
R27(1Bh)
Additional
Control (3)
R8 (08h)
Clocking and
Sample Rate
Control
REGISTER
ADDRESS
REGISTER
ADDRESS
‘Normal’ mode supports master clocks of 128f
(Note: f
USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in
systems with a USB interface, and eliminates the need for an external PLL to generate
another clock frequency for the audio codec.
s
refers to the ADC or DAC sample rate, whichever is faster)
[8:7] ADCLRM
BIT
6
5:1
0
BIT
LABEL
[1:0]
CLKDIV2
SR [4:0]
USB
DEFAULT
LABEL
00
Configures ADCLRC pin
00 = ADCLRC is ADC word clock input (slave
mode) or ADCLRC output (master mode)
01 = ADCLRC pin is MCLK output
10 = ADCLRC pin is MCLK / 5.5 output
11 = ADCLRC pin is MCLK / 6 output
0
00000
0
s
DEFAULT
, 192f
s
, 256f
s
, 384f
DESCRIPTION
Master Clock Divide by 2
1 = MCLK is divided by 2
0 = MCLK is not divided
Sample Rate Control
Clocking Mode Select
1 = USB Mode
0 = ‘Normal’ Mode
s
, and their multiples
PD Rev 4.0 August 2008
DESCRIPTION
WM8987L
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