wm8987 Wolfson Microelectronics plc, wm8987 Datasheet - Page 45

• Manufacturer Part Number: wm8987
• Description: Stereo Codec For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

Production Data
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POWER MANAGEMENT
The WM8987L has two control registers that allow users to select which functions are active. For
minimum power consumption, unused functions should be disabled. To avoid any pop or click noise,
it is important to enable or disable functions in the correct order (see Applications Information).
VMIDSEL is the enable for the VMID reference, which defaults to disabled and can be enabled as a
50kΩ potential divider or, for low power maintenance of VREF when all other blocks are disabled, as
a 500kΩ potential divider.
Table 41 Power Management
STOPPING THE MASTER CLOCK
In order to minimise power consumed in the digital core of the WM8987L, the master clock may be
stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the
DIGENB bit (R25, bit 0) can be set to stop the MCLK signal from propagating into the device core. In
Standby mode, setting DIGENB will typically provide an additional power saving on DCVDD of 20uA.
However, since setting DIGENB has no effect on the power consumption of other system
components external to the WM8987L, it is preferable to disable the master clock at its source
wherever possible.
Table 42 ADC and DAC Oversampling Rate Selection
Note: Before DIGENB can be set, the control bits ADCL, ADCR, DACL and DACR must be set to
zero and a waiting time of 1ms must be observed. Any failure to follow this procedure may prevent
DACs and ADCs from re-starting correctly.
R25 (19h)
Additional Control
(1)
R25 (19h)
Power
Management
(1)
R26 (1Ah)
Power
Management
(2)
Notes:
1. All bits except VMIDSEL are 1=on, 0=off.
2. The left mixer is enabled when LOUT2=1.
3. The right mixer is enabled when ROUT1=1 or ROUT2=1.
4. The mono mixer is enabled when MONO=1.
REGISTER
ADDRESS
REGISTER
ADDRESS
8:7
6
5
4
3
2
1
8
7
5
4
3
2
1
BIT
0
BIT
VMIDSEL
VREF
AINL
AINR
ADCL
ADCR
MICB
DACL
DACR
ROUT1
LOUT2
ROUT2
MONO
OUT3
LABEL
DIGENB
LABEL
00
0
0
0
0
0
0
0
0
0
0
0
0
0
DEFAULT
0
DEFAULT
Vmid divider enable and select
00 – Vmid disabled (for OFF mode)
01 – 50kΩ divider enabled (for
10 – 500kΩ divider enabled (for low-power
11 – 5kΩ divider enabled (for fast start-up)
VREF (necessary for all other functions)
Analogue in PGA Left
Analogue in PGA Right
ADC Left
ADC Right
MICBIAS
DAC Left
DAC Right
ROUT1 Output Buffer
LOUT2 Output Buffer
ROUT2 Output Buffer
Mono Mixer
OUT3 Output Buffer
playback/record)
standby)
Master clock disable
0: master clock enabled
1: master clock disabled
DESCRIPTION
DESCRIPTION
PD Rev 4.0 August 2008
WM8987L
45