wm8918 Wolfson Microelectronics plc, wm8918 Datasheet - Page 40

• Manufacturer Part Number: wm8918
• Description: Ultra Low Power Dac For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

WM8918
DIGITAL MICROPHONE INTERFACE
Figure 27 Digital Microphone Interface
w
CHAN
CHAN
CHAN
CHAN
Mic (1)
Mic (1)
Mic (2)
Mic (2)
Right
Right
Left
Left
VDD
VDD
VDD
VDD
Data
CLK
Data
CLK
Data
CLK
Data
CLK
The WM8918 supports a stereo digital microphone interface. This may be provided on DMICDAT1 or
on DMICDAT2, as selected by the DMIC_SRC register bit. The analogue signal path from the
selected input pin must be disabled when using the digital microphone interface; this is achieved by
disabling the associated input PGA.
The two-channel audio data is multiplexed on the selected input pin. The associated clock,
DMICCLK, is provided on a GPIO pin.
The Digital Microphone Input is selected as input by setting the DMIC_ENA bit. The Digital
Microphone DSP functions are enabled by setting DMICL_ENA and DMICR_ENA for the left and
right channels respectively. The correct Digital Microphone sampling rate must be selected by setting
the DMIC_OSR128 register to 0.
The digital microphone interface configuration is illustrated in Figure 27.
Note that care must be taken to ensure that the respective digital logic levels of the microphone are
compatible with the digital input thresholds of the WM8918. The digital input thresholds are
referenced to DBVDD, as defined in “Electrical Characteristics”. It is recommended to power the
digital microphones from DBVDD.
When a GPIO pin is configured as DMIC Clock output, the WM8918 outputs a clock, which supports
Digital Microphone operation at a multiple of the device sampling rate, in the range 1-3MHz. The
Digital Micropone DSP must be enabled (see Table 8) and the sampling rate must be set in order to
ensure correct operation of all DSP functions associated with the digital microphone. Volume control
for the Digital Microphone Interface signals is provided using the registers described in Table 9.
See “General Purpose Input/Output (GPIO)” for details of configuring the DMICCLK output. See
“Clocking and Sample Rates” for details of the supported clocking configurations.
When the DMIC_ENA bit is set, then the IN1L/DMICDAT1 or IN1R/DMICDAT2 pin is used as the
digital microphone input DMICDAT. Up to two microphones can share each pin; the two microphones
are interleaved as illustrated in Figure 28.
DMICDAT1
DMICDAT2
GPIO 1/4
GPIO 1/4
IN1R/
IN1L/
DBVDD
DBVDD
AVDD
AVDD
DMIC_ENA
DMIC_ENA
DMIC_SRC
DBVDD
Notes:
- observe DMIC supply voltage range and logic levels
- 0.7*AVDD <= DBVDD <= AVDD
Interface
DMIC
Decimation
GPIO
HPF
DRC
PD, Rev 4.0, September 2010
Volume
DMIC
Production Data
Digital Audio
(AIFTXDAT)
Interface
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