wm8918 Wolfson Microelectronics plc, wm8918 Datasheet - Page 97

• Manufacturer Part Number: wm8918
• Description: Ultra Low Power Dac For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

Production Data
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OPCLK CONTROL
A clock output (OPCLK) derived from SYSCLK may be output on a GPIO pin. This clock is enabled
by register bit OPCLK_ENA, and its frequency is controlled by OPCLK_DIV.
This output of this clock is also dependent upon the GPIO register settings described under “General
Purpose Input/Output (GPIO)”.
Table 60 OPCLK Control
TOCLK CONTROL
A slow clock (TOCLK) is derived from the internally generated 256kHz clock to enable input de-
bouncing and volume update timeout functions. This clock is enabled by register bit TOCLK_ENA,
and its frequency is controlled by TOCLK_RATE and TOCLK_RATE_X4, as described in Table 61.
Table 61 TOCLK Control
R22 (16h)
Clock Rates 2
R26 (1Ah)
Audio
Interface 2
R22 (16h)
Clock Rates 2
R20 (14h)
Clock Rates 0
REGISTER
REGISTER
ADDRESS
ADDRESS
11:8
BIT
BIT
12
14
13
3
0
TOCLK_RATE_
TOCLK_RATE_
OPCLK_DIV [3:0]
TOCLK_RATE
TOCLK_ENA
OPCLK_ENA
LABEL
DIV16
LABEL
X4
DEFAULT
DEFAULT
0
0
0
0
0000
0
TOCLK Rate Divider (/2)
0 = f / 2
1 = f / 1
Zero Cross timeout enable
0 = Disabled
1 = Enabled
TOCLK Rate Divider (/16)
0 = f / 1
1 = f / 16
TOCLK Rate Multiplier
0 = f x 1
1 = f x 4
GPIO Clock Output Enable
0 = disabled
1 = enabled
GPIO Output Clock Divider
0000 = SYSCLK
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK / 16
1001 to 1111 = Reserved
PD, Rev 4.0, September 2010
DESCRIPTION
DESCRIPTION
WM8918
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