wm8742 Wolfson Microelectronics plc, wm8742 Datasheet - Page 25

• Manufacturer Part Number: wm8742
• Description: 24-bit 192khz Dac With Advanced Digital Filtering
• Manufacturer: Wolfson Microelectronics plc

Production Data
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Table 11 Typical Relationships Between Master Clock Frequency and Sampling Rate in normal
PCM mode
8FS MODE
Operation in 8FS mode requires that audio data for left and right channels is input separately on two
pins. DINR (pin 4) is the input for right channel data and DINL (pin 2) is the input for left channel
data. Hardware control of the device is not available.
The data can be input in two formats (left or right justified), selectable by register FMT[1:0], and two
word lengths (20 or 24 bit), selectable by register IWL[1:0]. In both modes the data is clocked into the
WM8742 MSB first.
For left justified data the word start is identified by the falling edge of LRCLK. The data is clocked in
on the next 20/24 BCLK rising edges. This format is compatible with industry-standard DSPs and
decoders such as the PMD100.
Figure 19 8FS Mode Left Justified Timing Requirements
For right justified mode, the data is justified to the rising edge of LRCLK and the data is clocked in on
the preceding 20/24 BCLK rising edges before the LRCLK rising edge. This format is compatible with
industry standard DSPs and decoders such as the DF1704 or SM5842.
Figure 20 8FS Mode Right Justified Timing Requirements
SAMPLING
176.4kHz
(LRCLK)
44.1kHz
88.2kHz
192kHz
32kHz
48kHz
96kHz
RATE
Unavailable
Unavailable
Unavailable
11.2896
22.5792
12.288
24.576
128fs
Unavailable
Unavailable
Unavailable
16.9344
33.8688
MASTER CLOCK (MCLK) FREQUENCY (MHZ)
18.432
36.864
192fs
Unavailable Unavailable Unavailable Unavailable
Unavailable Unavailable Unavailable Unavailable
11.2896
22.5792
12.288
24.576
8.192
256fs
16.9344
33.8688
12.288
18.432
36.864
384fs
PD, Rev 4.2, August 2009
Unavailable Unavailable
Unavailable Unavailable
22.5792
16.384
24.576
512fs
WM8742
33.8688
24.576
36.864
768fs
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