wm8569seds-v Wolfson Microelectronics plc, wm8569seds-v Datasheet - Page 20
![no-image](/images/no-image-200.jpg)
wm8569seds-v
Manufacturer Part Number
wm8569seds-v
Description
24-bit, 192khz Stereo Codec With Volume Control
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM8569SEDS-V.pdf
(36 pages)
- Current page: 20 of 36
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WM8569
w
The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of
ADCBCLK following a low to high ADCLRC transition and may be sampled on the rising edge of
ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 17)
Figure 17 DSP Mode A Timing Diagram – ADC Data Output
DSP MODE B
In DSP mode B, the MSB of DAC left channel data is sampled by the WM8569 on the first
DACBCLK rising edge following a DACLRC rising edge. (Figure 18).
Figure 18 DSP Mode B Timing Diagram – DAC Data Input
The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of
ADCBCLK as the low to high ADCLRC transition and may be sampled on the rising edge of
ADCBCLK. The right channel ADC data is contiguous with the left channel data (Figure 19).
Figure 19 DSP Mode B Timing Diagram – ADC Data Output
ADCLRC
ADCBCLK
ADCLRC
DOUT
DOUT
BCK
MSB
1
Input Word Length (IWL)
MSB
1 BCLK
LEFT CHANNEL
2
1
Input Word Length (IWL)
2
LEFT CHANNEL
n-1
LSB
n
n-1
LSB
1
n
RIGHT CHANNEL
2
1
RIGHT CHANNEL
2
n-1
n
n-1
1/fs
n
1/fs
NO VALID DATA
NO VALID DATA
PD Rev 4.0 June 2006
Production Data
1 BCLK
1
20
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