wm9711lgefl-v Wolfson Microelectronics plc, wm9711lgefl-v Datasheet - Page 43

• Manufacturer Part Number: wm9711lgefl-v
• Description: Low Power Audio Codec For Portable Applications
• Manufacturer: Wolfson Microelectronics plc

Production Data
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POWER MANAGEMENT
Table 30 Additional Functionality for GPIO Pins
The WM9711L includes the standard power down control register defined by the AC’97 specification
(register 26h). Additionally, it also allows more specific control over the individual blocks of the device
through register 24h. Each particular circuit block is ON when both the relevant bit in register 26h and
the relevant bit in register 24h are set to ‘0’.
Table 31 Powerdown and Status Register (Conforms to AC’97 Rev 2.2)
As can be seen from the table above, most blocks are ‘ON’ by default. However, if pin 47
(GPIO4/ADA/MASK) is held high during reset, the WM9711L starts up with all blocks powered down
by default, saving power. This is achieved by connecting a pull-up resistor (e.g. 100kΩ) from pin 47
to DBVDD. Note that the state of pin 47 during reset only affects register 26h.
58h
Additional
Functional
Control
26h
Powerdown/
Status
register
REGISTER
REGISTER
ADDRESS
ADDRESS
0
1
BIT
BIT
14
13
12
11
10
9
8
3
2
1
0
IRQ INV
WAKEEN
LABEL
LABEL
DAC
ADC
PR6
PR5
PR4
PR3
PR2
PR1
PR0
REF
ANL
NORMAL
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0
0
DEFAULT
1
1
1
1
DEFAULT
PIN 47 ‘HI’
DURING
1 (OFF)
1 (OFF)
1 (OFF)
1 (OFF)
1 (OFF)
1 (OFF)
1 (OFF)
RESET
Inverts the IRQ signal (pin 45)
0: IRQ signal not inverted
1: IRQ signal inverted
Enables GPIO wake-up
0: Disabled
1: Enabled
0
0
0
0
Disables HPOUTL, HPOUTR and
OUT3 Buffer
Disables internal clock
Disables AC-link interface
(external clock off)
Disables VREF, analogue mixers
and outputs
Disables analogue mixers,
LOUT2, ROUT2 (but not VREF)
Disables stereo DAC
Disables audio ADCs and input
Mux
Read-only bit, indicates VREF is
ready (inverse of PR2)
Read-only bit, indicates analogue
mixers are ready (inverse of PR3)
Read-only bit, indicates audio
DACs are ready (inverse of PR1)
Read-only bit, indicates audio
ADCs are ready (inverse of PR0)
DESCRIPTION
DESCRIPTION
PD Rev 4.3 August 2006
WM9711L
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