isppac-powr6at6 Lattice Semiconductor Corp., isppac-powr6at6 Datasheet - Page 17

• Manufacturer Part Number: isppac-powr6at6
• Description: In-system Programmable Power Supply Monitoring And Margining Controller
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
trim will begin and CLTLOCK/SMBA will only reassert when the trim process is complete. Contents of the I
cltlock_status register (0x00), however are not fully reset to initial conditions until the CLTLOCK/SMBA pin achieves
a reasserted state.
CAUTION: Issuing a RESET command through I
results in the device aborting all operations and returning to the power-on reset state except for the one condition
mentioned above.
I
I
devices on a circuit board. The ispPAC-POWR6AT6 supports a 7-bit addressing of the I
col, as well as SMBTimeout and SMBAlert features of the SMBus, enabling it to easily integrated into many types
of modern power management systems. Figure 12 shows a typical I
POWR6AT6s are slaved to a supervisory microcontroller. SDA is used to carry data signals, while SCL provides a
synchronous clock signal. The SMBAlert line is only present in SMBus systems. The 7-bit I
POWR6AT6 is fully programmable through the JTAG port.
Figure 12. ispPAC-POWR6AT6 in I
In both the I
ter device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices.
The ispPAC-POWR6AT6 is configured as a slave device, and cannot independently coordinate data transfers.
Each slave device on a given I
addressing portion of the standard. Any 7-bit address can be assigned to the ispPAC-POWR6AT6 device by pro-
gramming through JTAG. When selecting a device address, one should note that several addresses are reserved
by the I
compatibility. Table 3 lists these reserved addresses.
2
2
C and SMBus are low-speed serial interface protocols designed to enable communications among a number of
C/SMBUS Interface
2
C and/or SMBus standards, and should not be assigned to ispPAC-POWR6AT6 devices to assure bus
SDA
V+
2
C and SMBus protocols, the bus is controlled by a single MASTER device at any given time. This mas-
MICROPROCESSOR
(I
2
SCL
C MASTER)
INTERRUPT
2
C bus is assigned a unique address. The ispPAC-POWR6AT6 implements the 7-bit
SDA/SMDAT (DATA)
SCL/SMCLK (CLOCK)
SMBALERT
2
C/SMBUS System
SDA
2
ispPAC-POWR6AT6
C or JTAG during the ispPAC-POWR6AT6 device operation,
(I
2
C SLAVE)
17
SCL
OUT5/
SMBA
2
C configuration, in which one or more ispPAC-
ispPAC-POWR6AT6 Data Sheet
SDA
ispPAC-POWR6AT6
(I
2
C SLAVE)
SCL
2
C communications proto-
OUT5/
SMBA
2
C address of the
To Other
Devices
I
2
C
2
C