isppac81 Lattice Semiconductor Corp., isppac81 Datasheet - Page 10

• Manufacturer Part Number: isppac81
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
SPI Power-On Condition
The SPI shift register is always reset to all zeroes when an ispPAC81 powers on. That means that if the ENSPI pin
is high at power on, the initial configuration will be set to a gain of 1X (0dB) and configuration “A” is selected as the
“wake-up” configuration. The only way to prevent this behavior would be to hold the ENSPI pin low while applying
power to the device. Because this is usually impractical, it is advised that if the ispPAC81 is used in SPI mode that
it be reloaded to the desired first configuration every time power is cycled to the device and/or that the “A” configu-
ration memory hold the desired “wake up” filter response.
A/B Configuration
Two complete configurations can be stored in the E
configuration in real time is accomplished with the device in the SPI interface mode (ENSPI pin = logic high). An
eight-bit string is read into the ispPAC81 in the following order: four “don’t care” bits followed by a CAL command
bit, the A/B configuration setting and gain bits PG2 and PG1.
Table 1. SPI Control Bit Sequence
Table 2. Gain Bit Settings
Table 3. JTAG User Configuration Bits
FreqRange Bit
UES Bits
Cap Bits
A/B Bit
PG1 & PG2 Bits
ESF
Symbol
Hi/Lo Frequency Range Bit Depending on the corner frequency, the frequency range bit is automatically set
Initial Configuration Select With the A/B bit set to “A” (a logic 0), the device will power up in the configura-
User Electronic Signature These are uncommitted E
Programmable Gain Bits
Electronic Security Fuse
Capacitor Selection Bits
Name
Bit 7
PG2
1X (0dB)
2X (6dB)
5X (14dB)
10X (20dB)
Bit 6
PG1
Gain Setting
from within PAC-Designer to optimize the transfer function response of the
ispPAC81. Exists for both the A and B user strings. Can be overridden from
within PAC-Designer from the edit symbol dialog.
future reference. The ispPAC81 contains 21 UES bits. These bits are accessible
from within PAC-Designer by using the Edit Symbol, UES Bits command. Part
of user configuration string A only.
Varying length data words for each of the seven configuration capacitors of the
ispPAC81. There is a complete set of 70 bits total for each user configuration
string, A and B.
tion stored in user string A. The designations of A or B would have been deter-
mined initially in the design environment using PAC-Designer. It is also possible
to designate the B user string as the initial or “wake up” configuration, although
this is not recommended as it blocks the algorithm required to do a “blind” veri-
fication of the A configuration of a previously programmed device. This is deter-
mined from within PAC-Designer in the edit symbol dialog.
Contained only in the A configuration string. Can also be modified under SPI
control. Refer to Table 2 for bit setting specifics.
Setting this bit causes all subsequent readouts of the device configuration to be
disabled (JTAG Verify commands). Can be reset by performing a JTAG user
(USRA) bulk erase commands and reprogramming the device. This feature is
used to prevent unauthorized readout of the device’s configuration.
Bit 5
A/B
Bit 4
CAL
2
memory of the ispPAC81. Selection of either the “A” or “B”
10
Bit 3
PG2
X
0
0
1
1
Bit 2
2
bits that can be used to store device information for
X
Description
Bit 1
PG1
X
0
1
0
1
Bit 0
X
ispPAC81 Data Sheet