isppac81 Lattice Semiconductor Corp., isppac81 Datasheet - Page 11

• Manufacturer Part Number: isppac81
• Description: In-system Programmable Analog Circuit
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
JTAG User Bits
There are a number of user-configured E
pull-down menus or directly in the schematic design entry screen of the PAC-Designer software interface to the
ispPAC81. See the online help associated with the ispPAC81 in PAC-Designer for more details of how to set/pro-
gram various operation modes. The list of control E
Differential I/O
Differential peak-peak voltage is determined by knowing the signal extremes on both differential input or output
pins. For example, if V(+) equals 4V and V(-) equals 1V, the differential voltage is defined as V(+) - V(-) = Vdiff, or
4V - 1V = +3V. Since either polarity can exist on differential I/O pins, it is also possible for the opposite extreme to
exist and would mean when V(+) equals 1V and V(-) equals 4V, the differential voltage is now 1V - 4V = -3V. To cal-
culate the differential peak-peak voltage or full signal swing, the absolute difference between the two extreme
Vdiff’s is calculated. Using the previous examples would result in |(+3V) - (-3V)| = 6V. It can be immediately seen
that true differential signals result in a doubling of usable dynamic range. For more explanation of this and other dif-
ferential circuit benefits, please refer to application note number AN6019, Differential Signaling.
Single-ended Input
To connect the ispPAC81 differential input to a single-ended signal, one of the differential inputs needs to be con-
nected to a DC bias, preferably VREF
the DC level of the other input. Since the input voltage is defined as V
The signal information is only present on one input, the other being connected to a voltage reference.
Single-ended Output
Connecting the output to a single-ended circuit is simpler still. Simply connect one-half of the differential output, but
not the other. Either output conveys the signal information, just at half the magnitude of the differential output. The
DC level of the single-ended output will be VREF
than VREF
voltage swing (3Vp-p versus 6Vp-p). If the load requires DC current, the available voltage swing is reduced. The
output is capable of 10mA, so any DC current raises the minimum allowable load impedance.
Input Common-Mode Voltage Range
For the ispPAC81, both maximum input signal range and corresponding common-mode voltage range are a func-
tion of the input gain setting. The maximum input voltage times the gain of an individual PACblock cannot exceed
the output range of that block or clipping will occur. The maximum guaranteed input range is 1V to 4V, with a typical
range of 0.7V to 4.3V for a 5V supply voltage.
The input common-mode voltage is V
input restrictions other than the previously mentioned clipping consideration. This is easily achieved when the input
signal is true differential and referenced to 2.5V.
When V
reached for a particular gain. The lowest V
0.584G·V
V
In Table 4, the maximum V
alent or greater value under the appropriate gain column and the widest range for V
across in the left-most two columns. Only a V
mance. Conversely, if the maximum V
the corresponding gain column. All values of V
CM
is V
CM
CM+
IN
OUT
is not 2.5V and the gain setting is greater than one, distortion will occur when the maximum input limit is
where G is the gain setting and V
= 5.0V - V
, the load draws a constant current. Using one of the differential outputs halves the available output
CM–
IN
where 5V is the nominal supply voltage.
for a given V
CM
OUT
CM
2
range is known, the largest acceptable peak value of V
. The input signal must either be AC coupled or have a DC bias equal to
= (V
CM–
CM
bits that control various aspects of and can all be accessed in either the
IN
for a given gain setting is expressed by the formula, V
CM+
to V
IN
CM
is the peak input voltage, expressed as |V
less than this will give full rated performance.
OUT
CM+
+ V
range equal to or less than this will give distortion-free perfor-
2
bits available is listed in Table 3.
. If the load is not AC coupled and is at a DC potential other
CM-
range is given. If the maximum V
11
)/2. When the value of V
IN+
- V
IN-
, the common mode level is ignored.
CM
CM
is 2.5V, there are no further
ispPAC81 Data Sheet
IN
IN+
will be found horizontally
is known, find the equiv-
- V
IN–
IN
| and the highest
CM–
can be found in
= 0.675V +