apa075 Actel Corporation, apa075 Datasheet - Page 68

• Manufacturer Part Number: apa075
• Description: Proasicplus Flash Family Fpgas
• Manufacturer: Actel Corporation

Asynchronous Write and Synchronous Read to the Same Location
Note: The plot shows the normal operation status.
Figure 1-38 • Asynchronous Write and Synchronous Read to the Same Location
Table 1-57 • T
1 -6 2
Symbol t
CCYC
CMH
CML
WBRCLKS
WBRCLKH
OCH
OCA
DWRRCLKS
DWRH
Notes:
1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.
2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write
3. A setup or hold time violation will result in unknown output data.
4. All –F speed grade devices are 20% slower than the standard numbers.
ProASIC
signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be
read.
PLUS
xxx
T
J
J
WB = {WRB + WBLKB}
Flash Family FPGAs
= 0°C to 110°C; V
= –55°C to 150°C, V
Cycle time
Clock high phase
Clock low phase
WB ↓ to RCLKS ↑ setup time
WB ↓ to RCLKS ↑ hold time
Old DO valid from RCLKS ↑
New DO valid from RCLKS ↑
DI to RCLKS ↑ setup time
DI to WB ↑ hold time
t DWRRCLKS
RCLKS
t BRCLKH
DD
DO
Description
t WRCKS
DI
DD
= 2.3 V to 2.7 V for Commercial/industrial
t OCH
t OCA
Last Cycle Data
= 2.3 V to 2.7 V for Military/MIL-STD-883
* New data is read if WB ↓ occurs before setup time.
The stored data is read if WB ↓ occurs after hold time.
t CMH
v5.5
Min.
–0.1
7.5
3.0
3.0
7.5
0
t CCYC
Max.
t CML
7.0
3.0
1.5
t
DWRH
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
New Data*
OCA/OCH
Access Timed Output
Notes
displayed
for