agl030 Actel Corporation, agl030 Datasheet
agl030
Manufacturer Part Number
agl030
Description
Igloo Low-power Flash Fpgas With Flash*freeze Technology
Manufacturer
Actel Corporation
Datasheet
1.AGL030.pdf
(194 pages)
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July 2008
© 2008 Actel Corporation
IGLOO Low-Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
High Capacity
Reprogrammable Flash Technology
In-System Programming (ISP) and Security
High-Performance Routing Hierarchy
IGLOO Product Family
IGLOO Devices
ARM-Enabled IGLOO Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals
I/O Banks
Maximum User I/Os
Package Pins
Notes:
1. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.
2. For higher densities and support of additional features, refer to the
3. Device/package support TBD.
4. AES is not available for ARM-enabled IGLOO devices.
5. The M1AGL250 device does not support this package.
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• 5 µW Power Consumption in Flash*Freeze Mode
• Low-Power Active FPGA Operation
• Flash*Freeze
• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze
• 15 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
• 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
• FlashLock
• Segmented, Hierarchical Routing and Clock Structure
CS
QFN
VQFP
FBGA
1 AGL015 and AGL030 devices do not support this feature.
Technology
Consumption while Maintaining FPGA Content
Mode
Standard (AES) Decryption (except ARM
devices) via JTAG (IEEE 1532–compliant)
®
to Secure FPGA Contents
handbook.
4
1
Technology
Enables
AGL015
QN68
15 k
128
384
1
1 k
49
5
6
2
–
–
–
–
Ultra-Low
®
-enabled IGLOO
UC81, CS81
AGL030
QN132
VQ100
30 k
Power
256
768
1 k
81
5
–
–
–
–
6
2
®
Advanced I/O
Clock Conditioning Circuit (CCC) and PLL
Embedded Memory
ARM Processor Support in IGLOO FPGAs
QN132
AGL060
FG144
VQ100
CS121
• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO Family
• Six CCC Blocks, One with an Integrated PLL
• Configurable
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit
• True Dual-Port SRAM (except ×18)
• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available
1,536
60 k
512
Yes
1 k
10
18
18
96
4
1
2
‡ Supported only by AGL015 and AGL030 devices.
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X
LVCMOS 2.5 V / 5.0 V Input
(AGL250 and above)
Capabilities, and External Feedback
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
with or without Debug
3
3
IGLOOe Low-Power Flash FPGAs with Flash*Freeze
AGL125
QN132
VQ100
FG144
CS196
125 k
1,024
3,072
Yes
133
1 k
16
36
18
8
1
2
Phase
M1AGL250
QN132
I/O
AGL250
CS196
VQ100
FG144
250 k
6,144
143
Yes
1 k
24
36
18
–
8
1
4
3,5
Standards:
5
1
Shift,
M1AGL600
AGL600
1
13,824
FG144,
FG256,
CS281
FG484
1
600 k
and Drive Strength
Multiply/Divide,
108
235
Yes
1 k
36
24
18
–
1
4
‡
LVTTL,
FG144, FG256,
M1AGL1000
AGL1000
1
24,576
FG484
CS281
1 M
144
300
Yes
1 k
53
32
18
1
4
–
LVCMOS
1 RAM
v1.1
1
Delay
, and
®
I
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